Availability  is  the  capability  of  a system to accept and successfully
   process an individual job.  Systems operating in accordance  with  ESA/390
   permit  substantial  availability by (1) allowing a large number and broad
   range of jobs to be processed concurrently, thus making the system readily
   accessible to any particular job, and (2) limiting the effect of an  error
   and  identifying more precisely its cause, with the result that the number
   of jobs affected by errors is minimized and the correction of  the  errors
   facilitated.

• A program is checked for the correctness of instructions and data as the program is executed, and program errors are indicated separate from equipment errors. Such checking and reporting assists in locating failures and isolating effects.

• The protection facilities, in conjunction with dynamic address translation and the separation of programs and data in different address spaces, permit the protection of the contents of storage from destruction or misuse caused by erroneous or unauthorized storing or fetching by a program. This provides increased security for the user, thus permitting applications with different security requirements to be processed concurrently with other applications.

• Dynamic address translation allows isolation of one application from another, still permitting them to share common resources. Also, it permits the implementation of virtual machines, which may be used in the design and testing of new versions of operating systems along with the concurrent processing of application programs. Additionally, it provides for the concurrent operation of incompatible operating systems.

• The use of access registers allows programs, data, and different collections of data to reside in different address spaces, and this further reduces the likelihood that a store using an incorrect address will produce either erroneous results or a system-wide failure.

• Multiprocessing and the channel subsystem permit better use of storage and processing capabilities, more direct communication between CPUs, and duplication of resources, thus aiding in the continuation of system operation in the event of machine failures.

• MONITOR CALL, program-event recording, and the timing facilities permit the testing and debugging of programs without manual intervention and with little effect on the concurrent processing of other programs.

• On most models, error checking and correction (ECC) in main storage, CPU retry, and command retry provide for circumventing intermittent equipment malfunctions, thus reducing the number of equipment failures.

• An enhanced machine-check-handling mechanism provides model-independent fault isolation, which reduces the number of programs impacted by uncorrected errors. Additionally, it provides model-independent recording of machine-status information. This leads to greater machine-check-handling compatibility between models and improves the capability for loading and operating a program on a different model when a system failure occurs.

• A small number of manual controls are required for basic system operation, permitting most operator-system interaction to take place via a unit operating as an I/O device and thus reducing the possibility of operator errors.

• The logical partitions made available by the PR/SM feature allow continued reliable production operations in one or more partitions while new programming systems are tested in other partitions. This is an advancement in particular for non-VM installations.

• The operational extensions and channel-subsystem-call facility of ESA/390 improve the ability to continue execution of application programs in the presence of system incidents and the ability to make configuration changes with less disruption to operations.

                            ___ 
                /__________|ETR|__________/
                           |_ _|
                             |
    __________________       |
   |                  |     _|_________        ______________ 
   |                  |    |           |______|              |
   |                  |____|    CPU    |__    |              |
   |                  |    |     ______|  |   |              |
   |                  |    |    |Vector|  |   |              |
   |                  |    |_ __|______|  |   |              |
   |                  |      |            |   |              |
   | Expanded Storage |     _|_________   |   | Main Storage |
   |                  |    |           |__|___|              |
   |                  |____|    CPU    |__|   |              |
   |                  |    |     ______|  |   |              |
   |                  |    |    |Crypto|  |   |              |
   |                  |    |____|______|  |   |              |
   |                  |                   |   |_______ ______|
   |                  |        ___________|           |
   |__________________|       |                       |
                              |    ___________________|
                              |   |
     _________________________|___|________________________ 
    |                                                      |
    |                        Channel                       |
    |                       Subsystem                      |
    |_ ___ ___ ______ ___ ________ _ _ _ ___ ______________|
      |...|...|......|...|        | | | |...|
      |   |   |      |   |        | | | |   |
      Serial Channel Paths   Parallel Channel Paths
      |   |   |      |   |        | | | |   |
      |   |   |      |   |        | | / /   |__________ _______/
      |  _|___|_    _|___|_       | |                  |
      | |Dynamic|  |Dynamic|      | |__ _________/     |
      | |Switch |  |Switch |      |   _|              _| 
      | |_ ___ _|  | _ ___ |      |  |CU|            |CU|_ _ _ _/
      |   |...|     | |...|       |  |_ |  _         |_ | O O O
      |   |   |_____| |   |       |    |__| |          |
      |   | ________|||   |       |     __| |_ _ _ _/  |
      |   ||         ||   |       |   _|  |_| O O O    |
      |_  ||         ||   |       |  |CU|              |
     |CU||CU|       |CU|  |       |  |_ |              |
     | _|| _|       | _|  |       |____|______ ________|_______/
      |   |          |    |_                 _| 
      |   |_ _ _ _/  |   |CU|_ _ _ _/       |CU|_ _ _ _/
      |     O O O    |   |__| O O O         |__| O O O
      |_ _ _ _/      |_ _ _ _/
        O O O          O O O

   Figure  2-1. Logical Structure of an ESA/390 System with Two CPUs

   A system viewed without regard to its I/O devices  is  referred  to  as  a
   configuration.      All   of   the  physical  equipment,  whether  in  the
   configuration or not, is referred to as the installation.

Subtopics:

• 2.1 Main Storage
• 2.2 Expanded Storage
• 2.3 CPU
• 2.4 External Time Reference
• 2.5 I/O
• 2.6 Operator Facilities

   Main  storage,  which  is  directly  addressable,  provides for high-speed
   processing of data by the CPUs and the channel subsystem.   Both data  and
   programs  must  be loaded into main storage from input devices before they
   can be processed.   The amount of main storage  available  on  the  system
   depends  on  the  model,  and,  depending  on the model, the amount in the
   configuration  may  be  under  control  of  model-dependent  configuration
   controls.    The  storage is available in multiples of 4K-byte blocks.  At
   any instant, the channel subsystem and all CPUs in the configuration  have
   access  to  the  same blocks of storage and refer to a particular block of
   main-storage locations by using the same absolute address.

   Expanded  storage may be available on some models.  Expanded storage, when
   available, can be accessed by all CPUs in the configuration  by  means  of
   instructions that transfer 4K-byte blocks of data from expanded storage to
   main storage or from main storage to expanded storage.  These instructions
   are  not described.   Another capability for accessing expanded storage is
   described in the definition of the MOVE  PAGE  instruction  in  Chapter 7,
   "General Instructions," and Chapter 10, "Control Instructions."

   The central processing unit (CPU) is the controlling center of the system.
   It  contains  the  sequencing  and  processing  facilities for instruction
   execution, interruption action, timing functions, initial program loading,
   and other machine-related functions.

Subtopics:

• 2.3.1 PSW
• 2.3.2 General Registers
• 2.3.3 Floating-Point Registers
• 2.3.4 Control Registers
• 2.3.5 Access Registers
• 2.3.6 Vector Facility
• 2.3.7 Cryptographic Facility

   The  program-status word (PSW) includes the instruction address, condition
   code, and other information used to control instruction sequencing and  to
   determine  the  state of the CPU.  The active or controlling PSW is called
   the current PSW.  It governs the program currently being executed.

   Instructions  may  designate  information  in  one  or  more of 16 general
   registers.  The general registers may be used  as  base-address  registers
   and  index  registers in address arithmetic and as accumulators in general
   arithmetic and logical operations.  Each register contains 32 bits.    The
   general registers are identified by the numbers 0-15 and are designated by
   a  four-bit  R  field  in  an instruction.   Some instructions provide for
   addressing multiple general registers by having several  R  fields.    For
   some  instructions,  the  use  of  a  specific general register is implied
   rather than explicitly designated by an R field of the instruction.

   Four floating-point registers are available for floating-point operations.
   They  are identified by the numbers 0, 2, 4, and 6 and are designated by a
   four-bit R field in  floating-point  instructions.    Each  floating-point
   register is 64 bits long and can contain either a short (32-bit) or a long
   (64-bit)  floating-point  operand.   A short operand occupies the leftmost
   bit positions of a floating-point register.  The rightmost portion of  the
   register  is  ignored  in  operations  that use short operands and remains
   unchanged in operations that produce short results.  Two pairs of adjacent
   floating-point registers can be used for extended operands:   registers  0
   and  2,  and  registers  4 and 6.   Each of these pairs, identified by the
   numbers 0 and 4, provides for a 128-bit format.

   The  CPU  has 16 control registers, each having 32 bit positions.  The bit
   positions in the registers are assigned to particular  facilities  in  the
   system,  such  as  program-event recording, and are used either to specify
   that an operation  can  take  place  or  to  furnish  special  information
   required by the facility.

   The  CPU  has  16  access  registers  numbered  0-15.   An access register
   consists of 32 bit positions containing  an  indirect  specification  (not
   described here in detail) of a segment-table designation.  A segment-table
   designation  is  a parameter used by the dynamic-address-translation (DAT)
   mechanism to translate references to a corresponding address space.   When
   the  CPU  is in a mode called the access-register mode (controlled by bits
   in the PSW), an instruction B field, used to specify a logical address for
   a storage-operand  reference,  designates  an  access  register,  and  the
   segment-table  designation specified by the access register is used by DAT
   for the reference being made.  For some instructions, an R field  is  used
   instead  of  a B field.  Instructions are provided for loading and storing
   the contents of the access registers and for moving the  contents  of  one
   access register to another.

   R Field     Control         Access            General             Floating-Point
     and      Registers       Registers         Registers              Registers
   Register
    Number  |_32 bits_ÿ|   |_32 bits_ÿ|     |_32 bits_ÿ|     |______64 bits______ÿ|

             ___________     ___________     _ ___________     _ _____________________ 
   0000  0  |           |   |           |   | |           |   | |                     |
            |___________|   |___________|   | |___________|   | |_____________________|
                                            |                 |
             ___________     ___________    |  ___________    |
   0001  1  |           |   |           |   | |           |   |
            |___________|   |___________|   |_|___________|   |
                                                              |
             ___________     ___________     _ ___________    |  _____________________ 
   0010  2  |           |   |           |   | |           |   | |                     |
            |___________|   |___________|   | |___________|   |_|_____________________|
                                            |
             ___________     ___________    |  ___________ 
   0011  3  |           |   |           |   | |           |
            |___________|   |___________|   |_|___________|

             ___________     ___________     _ ___________     _ _____________________ 
   0100  4  |           |   |           |   | |           |   | |                     |
            |___________|   |___________|   | |___________|   | |_____________________|
                                            |                 |
             ___________     ___________    |  ___________    |
   0101  5  |           |   |           |   | |           |   |
            |___________|   |___________|   |_|___________|   |
                                                              |
             ___________     ___________     _ ___________    |  _____________________ 
   0110  6  |           |   |           |   | |           |   | |                     |
            |___________|   |___________|   | |___________|   |_|_____________________|
                                            |
             ___________     ___________    |  ___________ 
   0111  7  |           |   |           |   | |           |
            |___________|   |___________|   |_|___________|

             ___________     ___________     _ ___________ 
   1000  8  |           |   |           |   | |           |
            |___________|   |___________|   | |___________|
                                            |
             ___________     ___________    |  ___________ 
   1001  9  |           |   |           |   | |           |
            |___________|   |___________|   |_|___________|

             ___________     ___________     _ ___________    Note:  The brackets
   1010 10  |           |   |           |   | |           |   indicate that the two
            |___________|   |___________|   | |___________|   registers may be coupled
                                            |                 as a double-register
             ___________     ___________    |  ___________    pair, designated by
   1011 11  |           |   |           |   | |           |   specifying the lower-
            |___________|   |___________|   |_|___________|   numbered register in
                                                              the R field.  For ex-
             ___________     ___________     _ ___________    ample, the general-
   1100 12  |           |   |           |   | |           |   register pair 14 and
            |___________|   |___________|   | |___________|   15 is designated by
                                            |                 1110 binary in the R
             ___________     ___________    |  ___________    field.
   1101 13  |           |   |           |   | |           |
            |___________|   |___________|   |_|___________|

             ___________     ___________     _ ___________ 
   1110 14  |           |   |           |   | |           |
            |___________|   |___________|   | |___________|
                                            |
             ___________     ___________    |  ___________ 
   1111 15  |           |   |           |   | |           |
            |___________|   |___________|   |_|___________|

   Figure  2-2. Control, Access, General, and Floating-Point Registers

   Depending  on the model, a vector facility may be provided as an extension
   of the CPU.  When the vector facility is provided on a CPU,  it  functions
   as an integral part of that CPU.  The functions of the vector facility and
   its  registers  are  described  in  the publication IBM Enterprise Systems
   Architecture/390 Vector Operations, SA22-7207.

   Depending  on  the  model,  an  integrated  cryptographic  facility may be
   provided as an extension of the CPU.  When the cryptographic  facility  is
   provided  on  a  CPU,  it  functions  as an integral part of that CPU.   A
   summary of  the  benefits  of  the  cryptographic  facility  is  given  in
   "Highlights  of  ESA/390"  in  topic 1.1;  the  facility  is otherwise not
   described.

   Depending  on the model, an external time reference (ETR) may be connected
   to the configuration.  A summary of the benefits of the ETR  is  given  in
   "Highlights  of  ESA/390"  in  topic 1.1;  the  facility  is otherwise not
   described.

   Input/output  (I/O) operations involve the transfer of information between
   main storage and an I/O device.   I/O  devices  and  their  control  units
   attach to the channel subsystem, which controls this data transfer.

Subtopics:

• 2.5.1 Channel Subsystem
• 2.5.2 Channel Paths
• 2.5.3 I/O Devices and Control Units

   I/O  devices  are  attached through control units to the channel subsystem
   via channel paths.  Control units may be attached to the channel subsystem
   via more than one channel path, and an I/O device may be attached to  more
   than one control unit.  In all, an individual I/O device may be accessible
   to  a  channel  subsystem  by  as  many  as eight different channel paths,
   depending on the model and the configuration.  The total number of channel
   paths provided by a  channel  subsystem  depends  on  the  model  and  the
   configuration; the maximum number of channel paths is 256.

• System/360 and System/370 I/O interface, called the parallel-I/O interface; the channel path is called a parallel channel path
• ESCON I/O interface, called the serial-I/O interface; the channel path is called a serial channel path

Each serial-I/O interface consists of two optical-fiber conductors between any two of a channel subsystem, a dynamic switch, and a control unit. A dynamic switch can be connected by means of multiple serial-I/O interfaces to either the same or different channel subsystems and to multiple control units. The number of control units which can be connected on one channel path depends on the channel-subsystem and dynamic-switch capabilities. Up to 256 devices can be attached to each control unit that uses the serial-I/O interface, depending on the control unit. The serial-I/O interface is described in the publication ESA/390 ESCON I/O Interface, SA22-7202.

   I/O  devices  include  such  equipment  as  printers, magnetic-tape units,
   direct-access-storage   devices,   displays,   keyboards,   communications
   controllers, teleprocessing devices, and sensor-based equipment.  Many I/O
   devices  function with an external medium, such as paper or magnetic tape.
   Other I/O devices handle only electrical signals, such as those  found  in
   displays  and communications networks.  In all cases, I/O-device operation
   is regulated by a control unit that provides  the  logical  and  buffering
   capabilities  necessary  to  operate  the associated I/O device.  From the
   programming  point  of  view,  most  control-unit  functions  merge   with
   I/O-device  functions.    The control-unit function may be housed with the
   I/O device or in the CPU, or a separate control unit may be used.

   The  operator  facilities  provide  the  functions  necessary for operator
   control of the machine.  Associated with the operator facilities may be an
   operator-console device, which may also be  used  as  an  I/O  device  for
   communicating with the program.

   This  chapter discusses the representation of information in main storage,
   as well as addressing, protection, and  reference  and  change  recording.
   The  aspects  of  addressing  which  are  covered  include  the  format of
   addresses, the concept of address spaces, the various types of  addresses,
   and  the manner in which one type of address is translated to another type
   of address.  A list of permanently assigned storage locations  appears  at
   the end of the chapter.

Subtopics:

• 3.1 Storage Addressing
• 3.2 Address Types and Formats
• 3.3 Storage Key
• 3.4 Protection
• 3.5 Reference Recording
• 3.6 Change Recording
• 3.7 Prefixing
• 3.8 Address Spaces
• 3.9 ASN Translation
• 3.10 ASN Authorization
• 3.11 Dynamic Address Translation
• 3.12 Address Summary
• 3.13 Assigned Storage Locations

   Storage  is  viewed  as  a  long  horizontal  string  of  bits.   For most
   operations, accesses to storage proceed in a left-to-right sequence.   The
   string  of bits is subdivided into units of eight bits.  An eight-bit unit
   is called a byte, which is the basic building  block  of  all  information
   formats.

Subtopics:

• 3.1.1 Information Formats
• 3.1.2 Integral Boundaries

   Information  is  transmitted  between  storage  and  a  CPU or the channel
   subsystem one byte, or a group of bytes, at  a  time.    Unless  otherwise
   specified,  a  group of bytes in storage is addressed by the leftmost byte
   of the group.   The number of bytes in the  group  is  either  implied  or
   explicitly specified by the operation to be performed.  When used in a CPU
   operation, a group of bytes is called a field.

   Certain  units  of information must be on an integral boundary in storage.
   A boundary is called integral for a unit of information when  its  storage
   address  is  a multiple of the length of the unit in bytes.  Special names
   are given to fields of two, four, and eight bytes on an integral boundary.
   A halfword is a group of two consecutive bytes on a two-byte boundary  and
   is  the  basic  building block of instructions.  A word is a group of four
   consecutive bytes on a four-byte boundary.   A doubleword is  a  group  of
   eight consecutive bytes on an eight-byte boundary.  (See Figure 3-1.)

               ·
               · ______ÿ Storage Addresses
               ·
               ·
                ___ ___ ___ ___ ___ ___ ___ ___ ___ _
   Bytes       | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | 8 |
               |___|___|___|___|___|___|___|___|___|_
               ·       ·       ·       ·       ·
               ·       ·       ·       ·       ·
               ·       ·       ·       ·       ·
                ___ ___ ___ ___ ___ ___ ___ ___ ___ _
   Halfwords   | 0     | 2     | 4     | 6     | 8
               |___|___|___|___|___|___|___|___|___|_
               ·               ·               ·
               ·               ·               ·
               ·               ·               ·
                ___ ___ ___ ___ ___ ___ ___ ___ ___ _
   Words       | 0             | 4             | 8
               |___|___|___|___|___|___|___|___|___|_
               ·                               ·
               ·                               ·
               ·                               ·
                ___ ___ ___ ___ ___ ___ ___ ___ ___ _
   Doublewords | 0                             | 8
               |___|___|___|___|___|___|___|___|___|_

   Figure  3-1. Integral Boundaries with Storage Addresses

Subtopics:

• 3.2.1 Address Types
• 3.2.2 Address Size and Wraparound
  

   For  purposes  of  addressing main storage, three basic types of addresses
   are  recognized:    absolute,  real,  and  virtual.    The  addresses  are
   distinguished  on the basis of the transformations that are applied to the
   address during a storage access.  Address translation converts virtual  to
   real,  and  prefixing converts real to absolute.  In addition to the three
   basic address types, additional types are defined which are treated as one
   or another of the three basic types, depending on the instruction and  the
   current mode.

Subtopics:

• 3.2.1.1 Absolute Address
• 3.2.1.2 Real Address
• 3.2.1.3 Virtual Address
• 3.2.1.4 Primary Virtual Address
• 3.2.1.5 Secondary Virtual Address
• 3.2.1.6 AR-Specified Virtual Address
• 3.2.1.7 Home Virtual Address
• 3.2.1.8 Logical Address
• 3.2.1.9 Instruction Address
• 3.2.1.10 Effective Address

   An  absolute  address  is the address assigned to a main-storage location.
   An  absolute  address  is  used  for  a   storage   access   without   any
   transformations performed on it.

   A real address identifies a location in real storage.  When a real address
   is  used  for  an  access  to  main  storage, it is converted, by means of
   prefixing, to an absolute address.

   A  virtual  address  identifies  a  location  in virtual storage.   When a
   virtual address is used for an access to main storage, it is translated by
   means of dynamic address translation to a  real  address,  which  is  then
   further converted by prefixing to an absolute address.

   A  primary  virtual address is a virtual address which is to be translated
   by means of the primary segment-table designation.  Logical addresses  are
   treated  as  primary  virtual  addresses  when  in the primary-space mode.
   Instruction addresses are treated as primary virtual addresses when in the
   primary-space mode, secondary-space mode, or access-register  mode.    The
   first-operand address of MOVE TO PRIMARY and the second-operand address of
   MOVE TO SECONDARY are always treated as primary virtual addresses.

   A secondary virtual address is a virtual address which is to be translated
   by  means  of  the secondary segment-table designation.  Logical addresses
   are treated as secondary virtual addresses  when  in  the  secondary-space
   mode.  The second-operand address of MOVE TO PRIMARY and the first-operand
   address  of  MOVE  TO  SECONDARY  are  always treated as secondary virtual
   addresses.

   An  AR-specified  virtual  address  is  a  virtual  address which is to be
   translated  by  means  of   an   access-register-specified   segment-table
   designation.  Logical addresses are treated as AR-specified addresses when
   in the access-register mode.

   A  home  virtual address is a virtual address which is to be translated by
   means of the  home  segment-table  designation.    Logical  addresses  and
   instruction  addresses  are  treated as home virtual addresses when in the
   home-space mode.

   Except  where  otherwise specified, the storage-operand addresses for most
   instructions are logical addresses.  Logical addresses are treated as real
   addresses  in  the  real  mode,  as  primary  virtual  addresses  in   the
   primary-space  mode, as secondary virtual addresses in the secondary-space
   mode, as AR-specified virtual addresses in the access-register  mode,  and
   as  home virtual addresses in the home-space mode.  Some instructions have
   storage-operand  addresses  or  storage  accesses  associated   with   the
   instruction  which  do not follow the rules for logical addresses.  In all
   such cases, the instruction definition contains a definition of  the  type
   of address.

   Addresses  used  to fetch instructions from storage are called instruction
   addresses.  Instruction addresses are treated as  real  addresses  in  the
   real  mode,  as  primary  virtual  addresses  in  the  primary-space mode,
   secondary-space  mode,  or  access-register  mode,  and  as  home  virtual
   addresses  in the home-space mode.  The instruction address in the current
   PSW and the target address of EXECUTE are instruction addresses.

   In  some situations, it is convenient to use the term "effective address."
   An effective address is the address which exists before any transformation
   by dynamic address translation or prefixing is performed.    An  effective
   address may be specified directly in a register or may result from address
   arithmetic.     Address  arithmetic  is  the  addition  of  the  base  and
   displacement or of the base, index, and displacement.

   Two sizes of addresses are provided:  24-bit and 31-bit.  A 24-bit address
   can  accommodate  a  maximum  of  16,777,216  (16M)  bytes;  with a 31-bit
   address, 2,147,483,648 (2G) bytes of storage can be addressed.

    ________ _______________________ 
   |        |     24-Bit Address    |
   |________|_______________________|
   0         8                     31

    _ ______________________________ 
   | |       31-Bit Address         |
   |_|______________________________|
   0  1                            31

   A  24-bit  virtual address is expanded to 31 bits by appending seven zeros
   on the left before it is translated by means of the  DAT  process,  and  a
   24-bit  real  address  is  similarly  expanded  to  31  bits  before it is
   transformed by prefixing.  A 24-bit absolute address  is  expanded  to  31
   bits  before  main  storage is accessed.   Thus, the 24-bit address always
   designates the first 16M-byte block of the 2G-byte storage addressable  by
   a 31-bit address.

Subtopics:

• 3.2.2.1 Address Wraparound

   The   CPU  performs  address  generation  when  it  forms  an  operand  or
   instruction address or when it generates the address of a table entry from
   the appropriate  table  origin  and  index.    It  also  performs  address
   generation  when  it increments an address to access successive bytes of a
   field.  Similarly, the channel subsystem performs address generation  when
   it  increments an address (1) to fetch a CCW, (2) to fetch an IDAW, (3) to
   transfer data, or (4) to compute the address of an I/O measurement block.

1. The carry out of the high-order bit position of the address is ignored. This handling of an address of excessive size is called wraparound.

2. An interruption condition is recognized.

Addresses generated by the CPU that may be virtual addresses always wrap. Wraparound also occurs when the linkage-stack-entry address in control register 15 is decremented below 0 by PROGRAM RETURN. For CPU table entries that are addressed by real or absolute addresses, it is unpredictable whether the address wraps or an addressing exception is recognized.

    _______________________________________________ _______ _______________ 
   |                                               |       | Handling When |
   |                                               |Address| Address Would |
   |        Address Generation for                 | Type  |     Wrap      |
   |_______________________________________________|_______|_______________|
   |Instructions and operands when AM is zero      |L,I,R,V|      W24      |
   |                                               |       |               |
   |Successive bytes of instructions and operands  |I,L,V¹ |      W24      |
   |  when AM is zero                              |       |               |
   |                                               |       |               |
   |Instructions and operands when AM is one       |L,I,R,V|      W31      |
   |                                               |       |               |
   |Successive bytes of instructions and operands  |I,L,V¹ |      W31      |
   |  when AM is one                               |       |               |
   |                                               |       |               |
   |DAT-table entries when used for implicit       |A or R²|      X31      |
   |  translation                                  |       |               |
   |                                               |       |               |
   |DAT-table entries when used for LRA            |A or R²|      X31      |
   |                                               |       |               |
 | |ASN-second-table, authority-table (during ASN  |   R   |      X31      |
 | |  authorization), linkage-table, and entry-    |       |               |
 | |  table entries                                |       |               |
 | |                                               |       |               |
 | |Authority-table (during access-register        |A or R²|      X31      |
 | |  translation) and access-list entries         |       |               |
   |                                               |       |               |
   |Linkage-stack entry                            |   V   |      W31      |
   |                                               |       |               |
   |I/O measurement block                          |   A   |      P31      |
   |                                               |       |               |
   |For a channel program with format-0 CCWs:      |       |               |
   |                                               |       |               |
   |  Successive CCWs                              |   A   |      P24      |
   |                                               |       |               |
   |  Successive IDAWs                             |   A   |      P24      |
   |                                               |       |               |
   |  Successive bytes of I/O data (without IDAWs) |   A   |      P24      |
   |                                               |       |               |
   |  Successive bytes of I/O data (with IDAWs)    |   A   |      P31      |
   |                                               |       |               |
   |For a channel program with format-1 CCWs:      |       |               |
   |                                               |       |               |
   |  Successive CCWs                              |   A   |      P31      |
   |                                               |       |               |
   |  Successive IDAWs                             |   A   |      P31      |
   |                                               |       |               |
   |  Successive bytes of I/O data (without IDAWs) |   A   |      P31      |
   |                                               |       |               |
   |  Successive bytes of I/O data (with IDAWs)    |   A   |      P31      |
   |_______________________________________________|_______|_______________|
    _______________________________________________________________________ 
   |Explanation:                                                           |
   |                                                                       |
   | ¹    Real addresses do not apply in this case since the instructions  |
   |      which designate operands by means of real addresses cannot des-  |
   |      ignate operands that cross boundaries 2²4 and 2³¹.               |
   | ²    It is unpredictable whether the address is absolute or real.     |
   | A    Absolute address.                                                |
   | AM   Addressing-mode bit in the PSW.                                  |
   | I    Instruction address.                                             |
   | L    Logical address.                                                 |
   | P24  An I/O program-check condition is recognized when the address    |
   |      exceeds 2²4 - 1 or is decremented below zero.                    |
   | P31  An I/O program-check condition is recognized when the address    |
   |      exceeds 2³¹ - 1 or is decremented below zero.                    |
   | R    Real address.                                                    |
   | V    Virtual address.                                                 |
   | W24  Wrap to location 0 after location 2²4 - 1 and vice versa.        |
   | W31  Wrap to location 0 after location 2³¹ - 1 and vice versa.        |
   | X31  When the address exceeds 2³¹ - 1, it is unpredictable whether    |
   |      the address wraps to location 0 after location 2³¹ - 1 or        |
   |      whether an addressing exception is recognized.                   |
   |_______________________________________________________________________|

   Figure  3-2. Address Wraparound

   A  storage  key  is  associated with each 4K-byte block of storage that is
   available in the configuration.  The storage key has the following format:

    ____ _ _ _ 
   |ACC |F|R|C|
   |____|_|_|_|
   0     4    6

   The bit positions in the storage key are allocated as follows:

   Four  protection  facilities  are provided to protect the contents of main
   storage from destruction or misuse by programs that contain errors or  are
   unauthorized:        key-controlled   protection,   access-list-controlled
   protection, page protection, and low-address protection.   The  protection
   facilities  are  applied  independently;  access  to  main storage is only
   permitted when none of the facilities prohibit the access.

Subtopics:

• 3.4.1 Key-Controlled Protection
• 3.4.2 Access-List-Controlled Protection
• 3.4.3 Page Protection
• 3.4.4 Low-Address Protection
• 3.4.5 Suppression on Protection

   When  key-controlled  protection  applies  to a storage access, a store is
   permitted only when the storage key matches the access key associated with
   the request for storage access; a fetch is permitted when the  keys  match
   or when the fetch-protection bit of the storage key is zero.

    _____________________________ __________________ 
   |          Conditions         |   Is Access to   |
   |________________ ____________|Storage Permitted?|
   |Fetch-Protection|            |_________ ________|
   |     Bit of     |            |         |        |
   |  Storage Key   |Key Relation|  Fetch  | Store  |
   |________________|____________|_________|________|
   |        0       |  Match     |   Yes   |  Yes   |
   |        0       |  Mismatch  |   Yes   |  No    |
   |        1       |  Match     |   Yes   |  Yes   |
   |        1       |  Mismatch  |   No    |  No    |
   |________________|____________|_________|________|
   |Explanation:                                    |
   |                                                |
   | Match   The four access-control bits of the    |
   |         storage key are equal to the access    |
   |         key, or the access key is zero.        |
   |                                                |
   | Yes     Access is permitted.                   |
   |                                                |
   | No      Access is not permitted.  On fetching, |
   |         the information is not made available  |
   |         to the program; on storing, the con-   |
   |         tents of the storage location are not  |
   |         changed.                               |
   |________________________________________________|

   Figure  3-3. Summary of Protection Action

• An interruption
• CPU logout
• Fetching of table entries for access-register translation, dynamic-address translation, PC-number translation, ASN translation, or ASN authorization
• Tracing
• A store-status function
• Storing in real locations 184-191 when TEST PENDING INTERRUPTION has an operand address of zero
• Initial program loading

Subtopics:

• 3.4.1.1 Storage-Protection-Override Control
• 3.4.1.2 Fetch-Protection-Override Control

   Bit  7  of  control register 0 is the storage-protection-override control.
   When the storage-protection-override facility is installed and this bit is
   set  to  one,  storage-protection  override   is   active.      When   the
   storage-protection-override  facility  is not installed or this bit is set
   to zero, storage-protection override is inactive.  When storage-protection
   override is active,  key-controlled  storage  protection  is  ignored  for
   storage  locations  having  an  associated  storage-key value of 9.   When
   storage-protection override is inactive, no special action is taken for  a
   storage-key value of 9.

   Programming Notes:

   Bit  6  of  control  register  0 is the fetch-protection-override control.
   When the bit  is  one,  fetch  protection  is  ignored  for  locations  at
   effective  addresses  0-2047.    An effective address is the address which
   exists  before  any  transformation  by  dynamic  address  translation  or
   prefixing.    However,  fetch  protection  is not ignored if the effective
   address is subject to dynamic address translation  and  the  private-space
   control,  bit  23,  is  one  in  the segment-table designation used in the
   translation.

   In  the  access-register  mode,  bit  6  of  the  access-list  entry,  the
   fetch-only bit, controls which types of operand references  are  permitted
   to  the  address space specified by the access-list entry.  When the entry
   is used in the access-register-translation part of a reference and  bit  6
   is zero, both fetch-type and store-type references are permitted; when bit
   6  is  one,  only  fetch-type  references are permitted, and an attempt to
   store causes a protection exception to be recognized and the execution  of
   the instruction to be suppressed.

   The  page-protection  facility controls access to virtual storage by using
   the page-protection bit in each page-table entry.  It provides  protection
   against improper storing.

   The   low-address-protection  facility  provides  protection  against  the
   destruction  of  main-storage  information  used   by   the   CPU   during
   interruption processing.  This is accomplished by prohibiting instructions
   from  storing  with  effective  addresses in the range 0 through 511.  The
   range criterion is applied before address transformation, if any,  of  the
   address  by  dynamic address translation or prefixing.  However, the range
   criterion is not applied, with the result that low-address protection does
   not apply,  if  the  effective  address  is  subject  to  dynamic  address
   translation  and  the  private-space  control,  bit  23,  is  one  in  the
   segment-table designation used in the translation.  Low-address protection
   does not apply  if  the  segment-table  designation  to  be  used  is  not
   available due to another type of exception.

   Programming Notes:

1. Low-address protection does not apply to storing performed by the channel subsystem, whereas key-controlled protection does.

2. Key-controlled protection does not apply to tracing, the second operand of TEST BLOCK, or instructions that operate specifically on the linkage stack, whereas low-address protection does.

   If  the  suppression-on-protection  facility  is installed, then, during a
   program interruption due to a protection exception, either a one or a zero
   is stored in bit position 29 of real locations 144-147.  The storing of  a
   one in bit position 29 indicates that:

• The unit of operation or instruction execution during which the exception was recognized was suppressed, except that, if the instruction execution would set the condition code if completed normally, the condition code is unpredictable.

• Bit positions 1-19 of real locations 144-147 contain bits 1-19 of the effective address that caused the exception. The effective address is the address which exists before any transformation by dynamic address translation (DAT) or prefixing. If the effective address was to be translated by DAT, bit positions 30 and 31 of real locations 144-147, and real location 160, contain the same information as is stored during a program interruption due to a page-translation exception--this information identifies the address space containing the protected address. If the effective address was not to be translated by DAT, the contents of bit positions 30 and 31 of real locations 144-147, and the contents of real location 160, are unpredictable. The contents of bit positions 0 and 20-28 of real locations 144-147 are always unpredictable.

• If an additional facility named the virtual-address enhancement of suppression on protection is installed (1), and if DAT was on, as indicated by the DAT-mode bit in the program old PSW, the effective address in real locations 144-147 is always one that was to be translated by DAT. (Bit 29 is set to zero if DAT was on but the effective address was not to be translated by DAT because it is a real address.)

   Programming Notes:

    _____ ____ _____ _____ ______ ____ __________ 
   |LA or|    |ALC  |     |Virt. |    |Bits 30,31|
   |Key- |    |or   |     |Addr. |    |and Loc.  |
   |Cont.|    |Page |Eff. |Enhmt.|Bit |160 if    |
   |Prot.|DAT |Prot.|Addr.|Instl.|29  |Bit 29 One|
   |_____|____|_____|_____|______|____|__________|
   | No  |On  | Yes |Log. |  -   | 1  |    P     |
   | Yes |On  | Yes |Log. |  -   | U1 |    P     |
   |     |    |     |     |      |    |          |
   | Yes |Off | No  |Log. |  -   | U2 |    U3    |
   | Yes |Off | No  |Real |  -   | U2 |    U3    |
   | Yes |On  | No  |Log. |  -   | U2 |    P     |
   | Yes |On  | No  |Real |  No  | U2 |    U3    |
   | Yes |On  | No  |Real |  Yes | 0A |    -     |
   |_____|____|_____|_____|______|____|__________|
   |Explanation:                                 |
   |                                             |
   |  -     Immaterial or not applicable.        |
   |  ALC   Access-list-controlled.              |
   |  LA    Low-address.                         |
   |  Log.  Logical.                             |
   |  P     Predictable.                         |
   |  U1    Unpredictable because low-address or |
   |        key-controlled protection may be     |
   |        recognized instead of access-list-   |
   |        controlled or page protection.       |
   |  U2    Unpredictable because bit 29 is only |
   |        required to be set to one for access-|
   |        list-controlled or page protection.  |
   |  U3    Unpredictable because effective      |
   |        address is not to be translated by   |
   |        DAT.                                 |
   |  0A    Zero because DAT is on and a virtual |
   |        effective address would not be       |
   |        stored.                              |
   |_____________________________________________|

   Figure  3-4. Suppression-on-Protection Results

   Reference  recording  provides  information for use in selecting pages for
   replacement.  Reference recording uses the reference bit,  bit  5  of  the
   storage  key.  The reference bit is set to one each time a location in the
   corresponding storage block is referred to either for fetching or  storing
   information, regardless of whether DAT is on or off.

• INSERT STORAGE KEY EXTENDED
• RESET REFERENCE BIT EXTENDED (reference bit is set to zero)
• SET STORAGE KEY EXTENDED (reference bit is set to a specified value)

   Change  recording  provides information as to which pages have to be saved
   in auxiliary storage when they are  replaced  in  main  storage.    Change
   recording uses the change bit, bit 6 of the storage key.

1. For the CPU, a store access is prohibited whenever an access exception exists for that access, or whenever an exception exists which is of higher priority than the priority of an access exception for that access.

2. For the channel subsystem, a store access is prohibited whenever a key-controlled-protection violation exists for that access.

Change recording does not take place for the operands of the following instructions since they directly modify a storage key without modifying a storage location:

• RESET REFERENCE BIT EXTENDED
• SET STORAGE KEY EXTENDED (change bit is set to a specified value)

   Prefixing  provides  the  ability  to  assign  the range of real addresses
   0-4095 (the prefix area) to a different block in absolute storage for each
   CPU, thus permitting more than one CPU sharing  main  storage  to  operate
   concurrently  with a minimum of interference, especially in the processing
   of interruptions.

    _ ___________________ ____________ 
   |/|      Prefix       |////////////|
   |_|___________________|____________|
   0  1                  20          31

   The  contents  of  the register can be set and inspected by the privileged
   instructions SET PREFIX and STORE PREFIX, respectively.  On setting,  bits
   corresponding  to  bit  positions  0  and 20-31 of the prefix register are
   ignored.  On storing, zeros are provided for these bit  positions.    When
   the  contents  of the prefix register are changed, the change is effective
   for the next sequential instruction.

1. Bits 1-19 of the address, if all zeros, are replaced with bits 1-19 of the prefix.

2. Bits 1-19 of the address, if equal to bits 1-19 of the prefix, are replaced with zeros.

3. Bits 1-19 of the address, if not all zeros and not equal to bits 1-19 of the prefix, remain unchanged.

Only the address presented to storage is translated by prefixing. The contents of the source of the address remain unchanged.

                         Prefixing                                 Prefixing
          _         _ _ _ _ _ _ _ _ _ _         _   _         _ _ _ _ _ _ _ _ _ _         _  
        |  |                                   |  |  |                                   |  |
        |  |______|_No Change___________|_____ÿ|  |  |      |                     |      |  |
        /  |                                   |  /  |                                   |  /
        | _|      | Apply               |      |_ |  |_____|___________No Change_|______|  |
        | 1|________Zeros_      ______________ÿ|2 |  |                                   |  |
        | _|      |       |    |        |      |_ |  |      |                     |      |  |
        /  |              |    |               |  /  |                                   |  /
        |  |      |       |    |        |      |  | _|      |               Apply |      |_ |
        |  |              |    |               |  | 2|______________      _Zeros________|1 |
        |  |      |       |    |        |      |  | _|      |        |    |       |      |_ |
        |  |              |____|____           |  |  |               |    |              |  |
        |  |      |            |    |   |      |  |  |      |        |    |       |      |  |
        /  |                   |    |          |  /  |           ____|____|              |  /
        |  |______|_No Change__|____|___|_____ÿ|  |  |      |   |    |            |      |  |
        |  |                   |    |          |  |  |          |    |                   |  |
        |  |      |            |    |   |      |  |  |_____|___|____|__No Change_|______|  |
        |  |                   |    |          |  |  |          |    |                   |  |
        |  |      |            |    |   |      |  |  |      |   |    |            |      |  |
        |  |                   |    |          |  |  |          |    |                   |  |
   4096 | _|      | Apply      |    |   | 4096 |_ | _|      |   |    |     Apply  |      |_ | 4096
        |  |________Prefix_____|    |_________ÿ|  |  |_________|    |_____Prefix________|  |
      0 | _|      | _ _ _ _ _ _ _ _ _ _ |    0 |_ | _|      | _ _ _ _ _ _ _ _ _ _ |      |_ | 0
   Real Addresses                              Absolute                             Real Addresses
   for CPU A                                   Addresses                            for CPU B


   (1)  Real addresses in which bits 1-19 are equal to the prefix for this CPU (A or B).

   (2)  Absolute addresses of the block that contains for this CPU (A or B) the real locations 0-4095.

   Figure  3-5. Relationship between Real and Absolute Addresses

   An  address  space  is  a consecutive sequence of integer numbers (virtual
   addresses), together with the  specific  transformation  parameters  which
   allow  each  number to be associated with a byte location in storage.  The
   sequence starts at zero and proceeds left to right.

Subtopics:

• 3.8.1 Changing to Different Address Spaces
• 3.8.2 Address-Space Number

   A  program  can  cause different address spaces to be addressable by using
   the semiprivileged SET ADDRESS SPACE CONTROL  instruction  to  change  the
   translation   mode   to  the  primary-space  mode,  secondary-space  mode,
   access-register mode, or home-space mode.    However,  SET  ADDRESS  SPACE
   CONTROL  can  set  the  home-space mode only in the supervisor state.  The
   program can cause still other address spaces to be  addressable  by  using
   other semiprivileged instructions to change the segment-table designations
   in  control  registers  1  and 7 and by using unprivileged instructions to
   change the contents of the access registers.   Only  the  privileged  LOAD
   CONTROL  instruction  is  available  for  changing  the home segment-table
   designation in control register 13.

   An  address  space  may  be  assigned an address-space number (ASN) by the
   control program.  The ASN designates, within a two-level  table  structure
   in  main  storage,  an ASN-second-table entry containing information about
   the address space.  If the ASN-second-table entry is marked as  valid,  it
   contains the segment-table designation that defines the address space.

   Control Register 4
   __ ________________ 
     |      PASN      |
   __|________________|
     16              31
   Control Register 3
   __ ________________ 
     |      SASN      |
   __|________________|
     16              31

   An  instruction  that  uses  ASN  translation  and  loads  the  primary or
   secondary segment-table designation into the appropriate control  register
   also loads the corresponding ASN into the appropriate control register.

   ASN translation is the process of translating the 16-bit ASN to locate the
   address-space-control  parameters.    ASN  translation may be performed as
   part of PROGRAM CALL with space switching (PC-ss), it is performed as part
   of PROGRAM TRANSFER with space switching (PT-ss)  and  SET  SECONDARY  ASN
   with  space  switching  (SSAR-ss), and it may be performed as part of LOAD
   ADDRESS SPACE  PARAMETERS.    For  PC-ss  and  PT-ss,  the  ASN  which  is
   translated  replaces  the primary ASN in control register 4.  For SSAR-ss,
   the ASN which is translated replaces the secondary ASN in control register
   3.  These two translation processes are called primary ASN translation and
   secondary ASN translation, respectively,  and  both  can  occur  for  LOAD
   ADDRESS  SPACE  PARAMETERS.    The ASN-translation process is the same for
   both primary and secondary ASN translation; only the uses of  the  results
   of the process are different.

   ASN
    __________ ______ 
   |   AFX    | ASX  |
   |__________|______|
   0          10    15

   The  AFX  is used to select an entry from the ASN first table.  The origin
   of the ASN first table is designated  by  the  ASN-first-table  origin  in
   control register 14.  The ASN-first-table entry contains the origin of the
   ASN  second table.  The ASX is used to select an entry from the ASN second
   table.  This entry contains the address-space-control parameters.

Subtopics:

• 3.9.1 ASN-Translation Controls
• 3.9.2 ASN-Translation Tables
• 3.9.3 ASN-Translation Process

   ASN  translation  is controlled by the ASN-translation-control bit and the
   ASN-first-table origin, both of which reside in control register 14.    It
   is  also  controlled  by the address-space-function-control bit in control
   register 0.

Subtopics:

• 3.9.1.1 Control Register 14
• 3.9.1.2 Control Register 0

   __ _ ____________________ 
     |T|        AFTO        |
   __|_|____________________|
     12                    31

• LOAD ADDRESS SPACE PARAMETERS
• PROGRAM CALL with space switching
• PROGRAM RETURN with space switching or when the restored SASN does not equal the restored PASN
• PROGRAM TRANSFER with space switching
• SET SECONDARY ASN

When the address-space-function-control bit in control register 0 is one, PROGRAM CALL with space switching (PC-ss) may omit performing ASN translation and instead obtain the address of an ASN-second-table entry directly from an entry-table entry. The ASN-translation control must be one whether or not PC-ss performs ASN translation; otherwise, a special-operation exception is recognized.

   Bit  15 of control register 0 is the address-space-function (ASF) control.
   When the ASF control is zero, the ASN-second table  begins  on  a  16-byte
   boundary,  an ASN-second-table entry has a length of 16 bytes, and PROGRAM
   CALL with space switching (PC-ss) always performs ASN translation.    When
   the ASF control is one, the ASN-second table begins on a 64-byte boundary,
   an  ASN-second-table  entry has a length of 64 bytes, and PC-ss may obtain
   an ASN-second-table-entry address from an entry-table entry instead of  by
   performing ASN translation.

   The  ASN-translation  process  consists  in  a  two-level lookup using two
   tables:  an ASN first table and an ASN second table.  These tables  reside
   in real storage.

Subtopics:

• 3.9.2.1 ASN-First-Table Entries
• 3.9.2.2 ASN-Second-Table Entries

   When  the  ASF control, bit 15 of control register 0, is zero, an entry in
   the ASN first table has the following format:

    _ ___________________________ ____ 
   |I|           ASTO            |0000|
   |_|___________________________|____|
   0  1                          28  31

   When the ASF control is one, an entry has the following format:

    _ _________________________ ______ 
   |I|           ASTO          |000000|
   |_|_________________________|______|
   0  1                        26    31

   When  the  ASF control in control register 0 is zero, the ASN-second-table
   entry has a length of 16 bytes.  When the ASF control is  one,  the  entry
   has  a  length  of  64 bytes.   The format of the 16-byte ASN-second-table
   entry is identical to that of the first 16 bytes  of  the  64-byte  entry.
   Only  the  first  16 bytes of the ASN-second-table entry (16-byte entry or
   64-byte entry) are used in or as a result of ASN translation.  The 16-byte
   ASN-second-table entry is described below.  The 64-byte entry as  used  by
   access-register  translation  for  other than the BRANCH IN SUBSPACE GROUP
   instruction  is  described  in  "Extended  ASN-Second-Table  Entries"   in
   topic 5.8.3.3.    The 64-byte entry as used by BRANCH IN SUBSPACE GROUP is
   described in "Subspace-Group ASN-Second-Table Entries" in topic 5.9.1.2.

    _ ___________________________ _ _ 
   |I|            ATO            |0|B|
   |_|___________________________|_|_|
   0  1                          30 31
    _______________ ____________ ____ 
   |      AX       |   ATL      |0000|
   |_______________|____________|____|
   32              48           60  63
    _______________STD_______________ 
    _ ______________ __ _ _ _ _______ 
   |X|      STO     |  |G|P|S|  STL  |
   |_|______________|__|_|_|_|_______|
   64               84 86    89     95
    _______________LTD_______________ 
    _ _______________________ _______ 
   |V|          LTO          |  LTL  |
   |_|_______________________|_______|
   96                        121   127

   The fields in the entry are allocated as follows:

Programming Note: The unused portion of the STD field, bits 84 and 85 of the AST entry, which corresponds to bits 20 and 21 of the STD, should be set to zeros. These bits are reserved for future expansion, and programs which place nonzero values in these bit positions may not operate compatibly on future machines.

   This  section  describes  the  ASN-translation  process as it is performed
   during the execution of the space-switching forms of PROGRAM CALL, PROGRAM
   RETURN, PROGRAM TRANSFER, and SET  SECONDARY  ASN,  and  also  in  PROGRAM
   RETURN when the restored secondary ASN does not equal the restored primary
   ASN.    ASN  translation  for  LOAD  ADDRESS SPACE PARAMETERS is the same,
   except that AFX-translation and ASX-translation exceptions do  not  occur;
   such  situations are instead indicated by the condition code.  Translation
   of an ASN is performed by means of two tables, an ASN first table  and  an
   ASN second table, both of which reside in main storage.

                                   ASN
         ____ _ _________       _____ ___ 
   CR14 |    |T|   AFTO  |     | AFX |ASX|
        |____|_|_____ ___|     |__ __|_ _|
              (x4096)|        (x4)|    |(xN)
                     |            |    |
    _________________|            |    |
   |                              |    |
   |       _______________________|    |
   |      |                            |
   |                                  |
   |      _   ASN First Table          |
   |____ÿ|+|  _________________        |
         | | |                 |       |
          |  |                 |       |
          |  |                 |       |
          |_ÿ|_ _____________ _|       |
          R  |I|     ASTO    |0|       |
             |_|______ ______|_|       |
             |        |(xN)    |       |
             |        |        |       |
             |________|________|       |
                      |                |
    __________________|                |
   |                                   |
   |       ____________________________|
   |      |
   |      
   |      _   ASN Second Table
   |____ÿ|+|  _____________________________________________________________________ 
         | | |                                                                     |
          |  |                                                                     |
          |  |                                                                     |
          |_ÿ|_ ____________ __ ________ ______ _ ________________ ________________|
          R  |I|      ATO   |0B|   AX   |  ATL |0|       STD      |      LTD       |*
             |_|____________|__|________|______|_|________________|________________|
             |                                                                     |
             |                                                                     |
             |_____________________________________________________________________|

          N:  16 if ASF control, bit 15 of control register 0, is zero; 64 if ASF
              control is one
          R:  Address is real
          *:  ASTE is 64 bytes if ASF control is one; last 48 bytes are not shown

   Figure  3-6. ASN Translation

Subtopics:

• 3.9.3.1 ASN-First-Table Lookup
• 3.9.3.2 ASN-Second-Table Lookup
• 3.9.3.3 Recognition of Exceptions during ASN Translation

   The  AFX  portion  of  the  ASN,  in  conjunction with the ASN-first-table
   origin, is used to select an entry from the ASN first table.

   The  ASX  portion  of  the  ASN,  in conjunction with the ASN-second-table
   origin contained in the ASN-first-table entry, is used to select an  entry
   from the ASN second table.

   The exceptions which can be encountered during the ASN-translation process
   are  collectively  referred  to as ASN-translation exceptions.   A list of
   these  exceptions  and   their   priorities   is   given   in   Chapter 6,
   "Interruptions."

   ASN authorization is the process of testing whether the program associated
   with   the  current  authorization  index  is  permitted  to  establish  a
   particular address space.  The ASN authorization is performed as  part  of
   PROGRAM  TRANSFER  with space switching (PT-ss) and SET SECONDARY ASN with
   space switching (SSAR-ss) and may be performed as  part  of  LOAD  ADDRESS
   SPACE   PARAMETERS.      ASN   authorization   is   performed   after  the
   ASN-translation process for these instructions.

Subtopics:

• 3.10.1 ASN-Authorization Controls
• 3.10.2 Authority-Table Entries
• 3.10.3 ASN-Authorization Process

   ASN  authorization uses the authority-table origin and the authority-table
   length from the ASN-second-table entry,  together  with  an  authorization
   index.

Subtopics:

• 3.10.1.1 Control Register 4
• 3.10.1.2 ASN-Second-Table Entry

   For  PT-ss and SSAR-ss, the current contents of control register 4 include
   the authorization index.  For LOAD ADDRESS SPACE  PARAMETERS  and  PROGRAM
   RETURN, the value which will become the new contents of control register 4
   is used.  The register has the following format:

    ________________ __
   |       AX       |
   |________________|__
   0               15

   The ASN-second-table entry which is fetched as part of the ASN translation
   process  contains  information  which  is  used to designate the authority
   table.  An entry in the ASN second table has the following format:

    _ ______________________________ __ 
   | |             ATO              |0B|
   |_|______________________________|__|
   0  1                               31
    _________________ ____________ ____ __
   |                 |    ATL     |0000|
   |_________________|____________|____|__
   32                48           60   64

   The  authority  table  consists  of entries of two bits each; accordingly,
   each byte of the authority table contains four entries  in  the  following
   format:

    __ __ __ __ 
   |PS|PS|PS|PS|
   |__|__|__|__|
   0           7

   The fields are allocated as follows:

   This  section  describes  the ASN-authorization process as it is performed
   during the execution of PROGRAM TRANSFER  with  space  switching  and  SET
   SECONDARY  ASN  with  space  switching.    For these two instructions, the
   ASN-authorization process is performed by using  the  authorization  index
   currently  in  control  register  4.   Secondary authorization for PROGRAM
   RETURN, when the restored  secondary  ASN  does  not  equal  the  restored
   primary  ASN,  and  for  LOAD ADDRESS SPACE PARAMETERS is the same, except
   that the value which will become the new contents of control register 4 is
   used  for  the  authorization  index.    Also,  for  LOAD  ADDRESS   SPACE
   PARAMETERS, a secondary-authority exception does not occur.  Instead, such
   a situation is indicated by the condition code.

                    _______ _______ 
               CR4 |  AX   |       |
                   |___ ___|_______|
                       |(x1/4)
                       |
          _____________|
         |
         |
         |    ASN Second Table
         |    _____________________________________________________________________ 
         |   |                                                                     |
         |   |                                                                     |
         |   |ASN-Second-Table Entry                                               |
         |   |_ ____________ __ ________ ______ _ ________________ ________________|
         |   |I|     ATO    |0B|   AX   |  ATL |0|       STD      |      LTD       |*
         |   |_|______ _____|__|________|______|_|________________|________________|
         |   |        |(x4)                                                        |
         |   |        |                                                            |
         |   |________|____________________________________________________________|
    _____|____________|
   |     |
   |     |
   |     |
   |     
   |     _   Authority Table
   |___ÿ|+|  ___ 
        | | |   |    For primary ASN authorization (PT-ss only):
         |  |   |      Primary-authority exception if P bit
         |  |   |      zero or table length exceeded.
         |_ÿ|_ _|
         R  |P|S|    For secondary ASN authorization (PR and SSAR-ss only):
            |_|_|      Secondary-authority exception if S bit
            |   |      zero or table length exceeded.
            |   |
            |___|    For secondary ASN authorization (LASP only):
                       Set condition code 2 if S bit zero or
                       table length exceeded.

         R:  Address is real
         *:  ASTE is 64 bytes if ASF control is one; last 48 bytes are not shown

   Figure  3-7. ASN Authorization

Subtopics:

• 3.10.3.1 Authority-Table Lookup
• 3.10.3.2 Recognition of Exceptions during ASN Authorization

   The  authorization  index,  in conjunction with the authority-table origin
   contained in the ASN-second-table entry, is used to select an  entry  from
   the authority table.

    ________________ ___________________________ 
   |                |     Bit Selected from     |
   |                |   Authority-Table Byte    |
   |                |         for Test          |
   | Authorization- |____________ ______________|
   |   Index Bits   |            |    S Bit     |
   |                |    P Bit   |   (SSAR-ss,  |
   |   14      15   |   (PT-ss)  | PR, or LASP) |
   |________________|____________|______________|
   |    0       0   |     0      |       1      |
   |                |            |              |
   |    0       1   |     2      |       3      |
   |                |            |              |
   |    1       0   |     4      |       5      |
   |                |            |              |
   |    1       1   |     6      |       7      |
   |________________|____________|______________|

   If the selected bit is one, the ASN is  authorized,  and  the  appropriate
   address-space-control  parameters  from  the AST entry are loaded into the
   appropriate control registers.  If the selected bit is zero,  the  ASN  is
   not  authorized, and a primary-authority exception is recognized for PT-ss
   or a secondary-authority exception is recognized for  SSAR-ss  or  PROGRAM
   RETURN.    For  LOAD  ADDRESS  SPACE  PARAMETERS,  when  the  ASN  is  not
   authorized, condition code 2 is set.

   The   exceptions   which   can   be  encountered  during  the  primary-and
   secondary-ASN-authorization processes and their priorities  are  described
   in  the  definitions  of  the  instructions  in which ASN authorization is
   performed.

   Dynamic  address  translation  (DAT) provides the ability to interrupt the
   execution of a program at an arbitrary moment, record it and its  data  in
   auxiliary  storage, such as a direct-access storage device, and at a later
   time return the program and the data to different  main-storage  locations
   for  resumption  of  execution.   The transfer of the program and its data
   between main and auxiliary storage may be  performed  piecemeal,  and  the
   return of the information to main storage may take place in response to an
   attempt  by  the  CPU to access it at the time it is needed for execution.
   These functions may be performed  without  change  or  inspection  of  the
   program  and  its data, do not require any explicit programming convention
   for the relocated program, and do not disturb the execution of the program
   except for the time delay involved.

    _ ___________ ________ ____________ 
   |/|    SX     |   PX   |     BX     |
   |_|___________|________|____________|
   0  1          12       20          31

Subtopics:

• 3.11.1 Translation Control
• 3.11.2 Translation Tables
• 3.11.3 Translation Process
• 3.11.4 Translation-Lookaside Buffer

   Address translation is controlled by three bits in the PSW and by a set of
   bits   referred  to  as  the  translation  parameters.    The  translation
   parameters are in control registers 0, 1, 7, and 13.  Additional  controls
   are located in the translation tables.

Subtopics:

• 3.11.1.1 Translation Modes
• 3.11.1.2 Control Register 0
• 3.11.1.3 Control Register 1
• 3.11.1.4 Control Register 7
• 3.11.1.5 Control Register 13

   The three bits in the PSW that control dynamic address translation are bit
   5,  the  DAT-mode bit, and bits 16 and 17, the address-space-control bits.
   When the DAT-mode bit is zero, then DAT is off, and the CPU is in the real
   mode.  When the DAT-mode bit is one, then DAT is on, and the CPU is in the
   translation  mode  designated  by  the  address-space-control  bits:    00
   designates the primary-space mode, 01 designates the access-register mode,
   10  designates  the secondary-space mode, and 11 designates the home-space
   mode.  The various modes are shown in Figure 3-8, along with the  handling
   of addresses in each mode.

    ________ ___ _____________________ _____________________ 
   |        |   |                     |Handling of Addresses|
   |PSW Bit |   |                     |___________ _________|
   |__ __ __|   |                     |Instruction| Logical |
   | 5|16|17|DAT|        Mode         | Addresses |Addresses|
   |__|__|__|___|_____________________|___________|_________|
   | 0| 0| 0|Off|Real mode            | Real      |Real     |
   | 0| 0| 1|Off|Real mode            | Real      |Real     |
   | 0| 1| 0|Off|Real mode            | Real      |Real     |
   | 0| 1| 1|Off|Real mode            | Real      |Real     |
   | 1| 0| 0|On |Primary-space mode   | Primary   |Primary  |
   |  |  |  |   |                     |   virtual |  virtual|
   | 1| 0| 1|On |Access-register mode | Primary   |AR-speci-|
   |  |  |  |   |                     |   virtual |  fied   |
   |  |  |  |   |                     |           |  virtual|
   | 1| 1| 0|On |Secondary-space mode | Primary   |Secondary|
   |  |  |  |   |                     |   virtual |  virtual|
   | 1| 1| 1|On |Home-space mode      | Home      |Home     |
   |  |  |  |   |                     |   virtual |  virtual|
   |__|__|__|___|_____________________|___________|_________|

   Figure  3-8. Translation Modes

   Six bits are provided in control register 0 for use in controlling dynamic
   address translation.  The bits are assigned as follows:

   __ _ __ _____ __ __
     |D|  | TF  |  |
   __|_|__|_____|__|__
      5    8    13

   The control bits are encoded as follows:
    _____________________________ _______ 
   |  Bits of Control Register 0 |       |
   |_____ _____ _____ _____ _____|       |
   |  8  |  9  |  10 |  11 |  12 | Valid |
   |_____|_____|_____|_____|_____|_______|
   |  1     0     1     1      0 |  Yes  |
   |                             |       |
   |  All others                 |  No   |
   |_____________________________|_______|

   When an invalid bit combination is  detected  in  bit  positions  8-12,  a
   translation-specification exception is recognized as part of the execution
   of an instruction using address translation.

   Control  register 1 contains the primary segment-table designation (PSTD).
   The register has the following format:

    _ __________________ __ _ _ _ _______ 
   | | Primary Segment- |  | | | |       |
   |X|   Table Origin   |  |G|P|S| PSTL  |
   |_|__________________|__|_|_|_|_______|
   0  1                 20 22    25     31

• A space-switch-event program interruption occurs when execution of the space-switching form of PROGRAM CALL (PC-ss), PROGRAM RETURN (PR-ss), or PROGRAM TRANSFER (PT-ss) is completed. The interruption occurs if bit 0 is one either before or after the operation.

• A space-switch-event program interruption occurs upon completion of a SET ADDRESS SPACE CONTROL instruction that changes the address space from which instructions are fetched either to or from the home address space; that is, when instructions are fetched from the home address space either before or after the operation but not both before and after the operation.

• Condition code 3 is set by LOAD ADDRESS SPACE PARAMETERS.

   Control  register  7  contains  the  secondary  segment-table  designation
   (SSTD).  The register has the following format:

    _ __________________ __ _ _ _ _______ 
   | |Secondary Segment-|  | | | |       |
   | |   Table Origin   |  |G|P|S| SSTL  |
   |_|__________________|__|_|_|_|_______|
   0  1                 20 22    25     31

   Control  register  13  contains the home segment-table designation (HSTD).
   The register has the following format:

    _ __________________ __ _ _ _ _______ 
   | |   Home Segment-  |  | | | |       |
   |X|   Table Origin   |  |G|P|S| HSTL  |
   |_|__________________|__|_|_|_|_______|
   0  1                 20 22    25     31

   Programming Notes:

   The  translation  process consists in a two-level lookup using two tables:
   a segment table and a page table.  These tables reside in real or absolute
   storage.

Subtopics:

• 3.11.2.1 Segment-Table Entries
• 3.11.2.2 Page-Table Entries
• 3.11.2.3 Summary of Segment-Table and Page-Table Sizes

   The entry fetched from the segment table has the following format:

    _ _________________________ _ _ ____ 
   |0|    Page-Table Origin    |I|C|PTL |
   |_|_________________________|_|_|____|
   0  1                        26  28  31

   The fields in the segment-table entry are allocated as follows:

   The entry fetched from the page table entry has the following format:

    _ ___________________ _ _ _ _ ________ 
   |0|       PFRA        |0|I|P|0|////////|
   |_|___________________|_|_|_|_|________|
   0  1                  20      24      31

   The fields in the page-table entry are allocated as follows:

   The sizes of segment tables and page tables are summarized in Figure 3-9.

    ________________________________________________________ 
   |                Segment-Table Parameters                |
   |_______ ____________ ________________________ __________|
   |       |            |     Corresponding      |          |
   |Virtual|            |     Segment Table      | Segment- |
   |Address| Number of  |____________ ___________|  Table   |
   | Size  | Addressable|  Maximum   |   Usable  |Increment |
   |(Bits) |  Segments  |Size (Bytes)|Length Code|  (Bytes) |
   |_______|____________|____________|___________|__________|
   |  24¹  |     16     |      64    |     0     |   --     |
   |  31   |  2,048     |   8,192    |   127     |   64     |
   |_______|____________|____________|___________|__________|

    ________________________________________________ 
   |            Page-Table Parameters²              |
   |____________ ________________________ __________|
   |            |     Corresponding      |          |
   |            |      Page Table        |  Page-   |
   | Number of  |____________ ___________|  Table   |
   |   Pages    |  Maximum   |  Usable   |Increment |
   | in Segment |Size (Bytes)|Length Code|  (Bytes) |
   |____________|____________|___________|__________|
   |    256     |   1,024    |    15     |   64     |
   |____________|____________|___________|__________|
   Explanation:

   ¹ A virtual address specified by the program in the 24-bit addressing mode
     consists of a 24-bit value embedded in a 31-bit address.

   ² The page-table size is independent of the virtual address size.



   Figure  3-9. Sizes of Segment Tables and Page Tables

   This  section  describes  the  translation  process  as  it  is  performed
   implicitly before a virtual  address  is  used  to  access  main  storage.
   Explicit  translation,  which  is  the  process of translating the operand
   address of LOAD REAL ADDRESS and TEST PROTECTION, is the same, except that
   segment-translation and page-translation exceptions  do  not  occur;  such
   situations  are  instead  indicated by the condition code.  Translation of
   the operand address of LOAD REAL ADDRESS also differs in that the CPU  may
   be in the real mode and the translation-lookaside buffer is not used.

Subtopics:

• 3.11.3.1 Effective Segment-Table Designation
• 3.11.3.2 Inspection of Control Register 0
• 3.11.3.3 Segment-Table Lookup
• 3.11.3.4 Page-Table Lookup
• 3.11.3.5 Formation of the Real Address
• 3.11.3.6 Recognition of Exceptions during Translation

   The segment-table designation used for a particular address translation is
   called  the  effective  segment-table  designation.    Accordingly, when a
   primary virtual address is translated, the contents of control register  1
   are  used  as  the effective segment-table designation.   Similarly, for a
   secondary virtual address, the contents of control register  7  are  used;
   for   an  AR-specified  virtual  address,  the  segment-table  designation
   specified by the access register is used; and for a home virtual  address,
   the contents of control register 13 are used.

      Control Register        ASN-Second Table
        1, 7, or 13                Entry                    Virtual Address
    ___________________      __________________            ______ ____ ______ 
   |PSTD, SSTD, or HSTD|    | AR-Specified STD |          |  SX  | PX |  BX  |
   |_________ _________|    |________ _________|          |___ __|_ __|___ __|
             |            _          |                    (x4)|    |(x4)  |
             |__________ÿ|1|________|                        |    |      |______ 
                         | |                                  |    |             |
                          |                                   |    |             |
                                                             |    |             |
              ___________°__ÿ________________                |    |             |
             |                                |               |    |             |
                                             |               |    |             |
    __________________         _______________|_____°_______|    |             |
      Effective STD           |               |                   |             |
    __________ ___ ___        |               |      |             |             |
   |    STO   |   |STL|       |               |      |             |             |
   |_____ ____|___|___|       |               |      |             |             |
         |(x4096)             |               |      |             |             |
    _____|                    |               |      |             |             |
   |                          |               |      |             |             |
   |       ___________________|          _____|______|_____________|             |
   |      |                             |     |      |                           |
   |                                   |     |      |                           |
   |      _   Segment Table             |     |      |                           |
   |____ÿ|+|  __________________        |     |      |                           |
         | | |                  |       |     |      |                           |
    _     |  |                  |       |     |      |                           |
   |4|    |_ÿ|____________ _ ___|       |     |      |                           |
   |_|   R/A |     PTO    | |PTL|       |     |      |                           |
             |______ _____|_|___|       |     |      |                           |
             |      |(x64)      |       |     |      |                           |
             |      |           |       |     |      |                           |
             |______|___________|       |     |      |                           |
                    |                   |     |      |                           |
    ________________|                   |     |      |                           |
   |                                    |           |                           |
   |                                         _      |                           |
   |       ____________________________°___ÿ|2|____|                           |
   |      |                                  | |         Translation             |
   |      |                                   |          Lookaside               |
   |                                         |          Buffer (TLB)            |
   |      _   Page Table                      |          ____________________    |
   |____ÿ|+|  __________________              |         |                    |   |
         | | |                  |      _______|_________|_____________       |   |
    _     |  |                  |     |       |         |                   |   |
   |4|    |_ÿ|__________ _______|     |       |________ÿ|_________ __________|   |
   |_|   R/A |    PFRA  |       |     |                 |         |   PFRA   |   |
             |_____ ____|_______|     |                 |_________|___ ______|   |
             |     |            |     |  _              |             |      |   |
             |     |            |     | |4|             |             |      |   |
             |_____|____________|     | |_|             |_____________|______|   |
                   |                  |                               |  _       |
                   |                  "                                |3|      |
                   |_________________ÿ°__ÿ___________________________ÿ° |_|      |
                                                          _                     
                                                         |4|      ________   ________ 
                                                         |_|      _________ _________ 
                                                                 |         |         |
                                                                 |_________|_________|
          R/A: Address is either real or absolute                    Real Address
     _ 
    |1| Control register 1 provides the primary segment-table designation for
    |_| translation of a primary virtual address, control register 7 provides
        the secondary segment-table designation for translation of a secondary
        virtual address, and control register 13 provides the home segment-table
        designation for translation of a home virtual address.  An ASN-second-
        table entry provides an AR-specified (access-register-specified) segment-
        table designation for translation of an AR-specified virtual address.

     _ 
    |2| Information, which may include portions of the virtual address and the
    |_| effective segment-table origin, is used to search the TLB.

     _ 
    |3| If a match exists, the page-frame real address from the TLB is used in
    |_| forming the real address.

     _ 
    |4| If no match exists, table entries in real or absolute storage are fetched.
    |_| The resulting fetched entries, in conjunction with the search information,
        are used to translate the address and may be used to form an entry in the
        TLB.

   Figure  3-10. Translation Process

   The  interpretation  of  the  virtual  address  for  translation  purposes
   requires that there be a valid translation format specified by  bits  8-12
   of  control  register  0.    If  bits  8-12  contain  an  invalid  code, a
   translation-specification exception is recognized.

   The  segment-index portion of the virtual address, in conjunction with the
   segment-table origin contained in the effective segment-table designation,
   is used to select an entry from the segment table.

   The  page-index  portion  of  the virtual address, in conjunction with the
   page-table origin contained in the segment-table entry, is used to  select
   an entry from the page table.

   When  no  exceptions  in  the  translation  process  are  encountered, the
   page-frame real  address  obtained  from  the  page-table  entry  and  the
   byte-index  portion  of  the  virtual  address  are concatenated, with the
   page-frame real address forming the leftmost part.  The result is the real
   storage address which corresponds to the virtual address.  All 31 bits  of
   the  address are used, regardless of whether the current PSW specifies the
   24-bit or 31-bit addressing mode.

   Invalid   addresses  and  invalid  formats  can  cause  exceptions  to  be
   recognized during the translation process.  Exceptions are recognized when
   information contained in control registers or table entries  is  used  for
   translation and is found to be incorrect.

Subtopics:

• 3.11.4.1 TLB Structure
• 3.11.4.2 Formation of TLB Entries
• 3.11.4.3 Use of TLB Entries
• 3.11.4.4 Modification of Translation Tables

   The   description   of  the  logical  structure  of  the  TLB  covers  the
   implementation by all systems operating as defined by ESA/390.    The  TLB
   entries  are  considered as being of two types:  TLB segment-table entries
   and TLB page-table entries.   A TLB  entry  is  considered  as  containing
   within  it  both  the information obtained from the table entry in real or
   absolute storage and the attributes used to fetch the entry from storage.

   The  formation  of  TLB  entries and the effect of any manipulation of the
   contents of a table entry in real  or  absolute  storage  by  the  program
   depend on whether the entry is attached to a particular CPU and on whether
   the entry is valid.

1. The current PSW specifies DAT on.

2. The current PSW contains no errors which would cause an early exception to be recognized.

3. The current translation format, bits 8-12 in control register 0, is valid.

4. The entry meets the requirements in a, b, c, or d below.
   1. The entry is within the segment table designated by the primary segment-table designation in control register 1, and the CPU is not in the home-space mode.

   2. The entry is within the segment table designated by the secondary segment-table designation in control register 7 and either of the following requirements is met:
      • The CPU is in the secondary-space mode or access-register mode.

      • The CPU is in the primary-space mode, and the secondary-space control, bit 5 of control register 0, is one.

   3. The entry is within a segment table for which the designation is in either an ALB ASN-second-table entry or an ASN-second-table entry which can be placed in the ALB, and the CPU is in the access-register mode. See "ART-Lookaside Buffer" in topic 5.8.5 for the meaning of the terminology used here.

   4. The entry is within the segment table specified by the home segment-table designation in control register 13, and the CPU is not in the secondary-space mode.

   The  usable  state  of a TLB entry denotes that the CPU can attempt to use
   the TLB entry for implicit address translation.  Also, the usable state of
   a TLB segment-table entry is a factor in determining whether a  page-table
   entry is attached.

1. The current PSW specifies DAT on.

2. The current PSW contains no errors which would cause an early exception to be recognized.

3. The current translation format, bits 8-12 in control register 0, is valid.

4. The TLB segment-table entry meets at least one of the following requirements:
   1. The common-segment bit is one in the TLB entry.

   2. The segment-table-origin field in the TLB entry is the same as the current PSTO, and the CPU is not in the home-space mode.

   3. The segment-table-origin field in the TLB entry is the same as the current SSTO, and either of the following requirements is met:
      • The CPU is in the secondary-space mode or access-register mode.

      • The CPU is in the primary-space mode, and the secondary-space control, bit 5 of control register 0, is one.

   4. The segment-table-origin field in the TLB entry is the same as one that can be obtained from an ASN-second-table entry by applying the access-register-translation process to the contents of an access register, and the CPU is in the access-register mode.

   5. The segment-table-origin field in the TLB entry is the same as the current HSTO, and the CPU is not in the secondary-space mode.

A TLB page-table entry is in the usable state when the page-table-origin field in the TLB page-table entry matches the page-table-origin field in a usable TLB segment-table entry or an attached and valid segment-table entry which would not cause a translation-specification exception if used for translation, and the page-index field in the TLB page-table entry is within the range permitted by the page-table-length field in the segment-table entry.

   Programming Notes:

   When an attached and invalid table entry is made valid and no usable entry
   for  the associated virtual address is in the TLB, the change takes effect
   no later than the end of the current unit of operation.   Similarly,  when
   an  unattached  and valid table entry is made attached and no usable entry
   for the associated virtual address is in the TLB, the change takes  effect
   no later than the end of the current unit of operation.

1. All entries are cleared from the TLB by the execution of PURGE TLB and SET PREFIX and by CPU reset.

2. Selected entries are cleared from all TLBs in the configuration by the execution of INVALIDATE PAGE TABLE ENTRY by any of the CPUs in the configuration.

3. Some or all TLB entries may be cleared at times other than those required by PURGE TLB, SET PREFIX, CPU reset, and INVALIDATE PAGE TABLE ENTRY.

1. INVALIDATE PAGE TABLE ENTRY should be executed before making any change to a page-table entry other than changing the rightmost byte; otherwise, the selective clearing portion of INVALIDATE PAGE TABLE ENTRY may not clear the TLB copies of the entry.

2. Invalidation of all the page-table entries within a page table by means of INVALIDATE PAGE TABLE ENTRY does not necessarily clear the TLB of the copies, if any, of the segment-table entry designating the page table. When it is desired to invalidate and clear the TLB of a segment-table entry, the rules in note 5 below must be followed.

3. When a large number of page-table entries are to be invalidated at a single time, the overhead involved in using PURGE TLB and in following the rules in note 5 below may be less than in issuing INVALIDATE PAGE TABLE ENTRY for each page-table entry.

1. A valid table entry must not be changed while it is attached to any CPU except either to invalidate the entry, by using INVALIDATE PAGE TABLE ENTRY, or to alter bits 24-31 of a page-table entry.

2. When any change is made to a table entry other than a change to bits 24-31 of a page-table entry, each CPU which may have a TLB entry formed from that entry must execute PURGE TLB or SET PREFIX or perform CPU reset, after the change occurs and prior to the use of that entry for implicit translation by that CPU, except that the purge is unnecessary if the change was made by using INVALIDATE PAGE TABLE ENTRY.

3. When any change is made to an invalid table entry in such a way as to allow intermediate valid values to appear in the entry, each CPU to which the entry is attached must execute PURGE TLB or SET PREFIX or perform CPU reset, after the change occurs and prior to the use of the entry for implicit address translation by that CPU.

4. When any change is made to a segment-table or page-table length, each CPU to which that table has been attached must execute PTLB after the length has been changed but before that table becomes attached again to the CPU.

The execution of PURGE TLB and SET PREFIX may have an adverse effect on the performance of some models. Use of these instructions should, therefore, be minimized in conformity with the above rules.

Subtopics:

• 3.12.1 Addresses Translated
• 3.12.2 Handling of Addresses
  

   Most  addresses  that are explicitly specified by the program and are used
   by the CPU to refer to storage are instruction or  logical  addresses  and
   are  subject  to  implicit  translation when DAT is on.   Analogously, the
   corresponding addresses indicated to the program on an interruption or  as
   the  result  of  executing  an  instruction  are  instruction  or  logical
   addresses.   The operand  address  of  LOAD  REAL  ADDRESS  is  explicitly
   translated, regardless of whether the PSW specifies DAT on or off.

   The handling of addresses is summarized in Figure 3-11.  This figure lists
   all  addresses  that  are  encountered  by  the  program and specifies the
   address type.

    _______________________________________________________________________ 
   | Virtual Addresses                                                     |
   |                                                                       |
   | · Address of storage operand for INSERT VIRTUAL STORAGE KEY           |
   | · Operand address in LOAD REAL ADDRESS                                |
   | · Addresses of storage operands for MOVE TO PRIMARY and MOVE TO       |
   |   SECONDARY                                                           |
   | · Address stored in the word at real location 144 on a program inter- |
   |   ruption for page-translation or segment-translation exception       |
   | · Linkage-stack-entry address in control register 15                  |
   | · Backward stack-entry address in linkage-stack header entry          |
   | · Forward-section-header address in linkage-stack trailer entry       |
   |                                                                       |
   | Instruction Addresses                                                 |
   |                                                                       |
   | · Instruction address in PSW                                          |
   | · Branch address                                                      |
   | · Target of EXECUTE                                                   |
   | · Address stored in the word at real location 152 on a program inter- |
   |   ruption for PER                                                     |
   | · Address placed in general register by BRANCH AND LINK, BRANCH AND   |
   |   SAVE, BRANCH AND SAVE AND SET MODE, BRANCH AND STACK, BRANCH IN     |
   |   SUBSPACE GROUP, BRANCH RELATIVE AND SAVE, and PROGRAM CALL          |
 | | · Address used in general register by BRANCH AND STACK.               |
 | | · Address placed in general register by BRANCH AND SET AUTHORITY      |
 | |   executed in reduced-authority state                                 |
   |                                                                       |
   | Logical Addresses                                                     |
   |                                                                       |
   | · Addresses of storage operands for instructions not otherwise        |
   |   specified                                                           |
   | · Address placed in general register 1 by EDIT AND MARK and TRANSLATE |
   |   AND TEST                                                            |
   | · Addresses in general registers updated by MOVE LONG, MOVE LONG      |
   |   EXTENDED, COMPARE LOGICAL LONG, and COMPARE LOGICAL LONG EXTENDED   |
   | · Addresses in general registers updated by CHECKSUM, COMPARE AND FORM|
   |   CODEWORD, and UPDATE TREE                                           |
   | · Address for TEST PENDING INTERRUPTION when the second-operand ad-   |
   |   dress is nonzero                                                    |
   |                                                                       |
   | Real Addresses                                                        |
   |                                                                       |
   | · Address of storage key for INSERT STORAGE KEY EXTENDED, RESET       |
   |   REFERENCE BIT EXTENDED, and SET STORAGE KEY EXTENDED                |
   | · Address of storage operand for LOAD USING REAL ADDRESS, STORE USING |
   |   REAL ADDRESS, and TEST BLOCK                                        |
   | · The translated address generated by LOAD REAL ADDRESS               |
   |_______________________________________________________________________|
    _______________________________________________________________________ 
   | Real Addresses (Continued)                                            |
   |                                                                       |
   | · Page-table origin in INVALIDATE PAGE TABLE ENTRY                    |
   | · Page-frame real address in page-table entry                         |
   | · Trace-entry address in control register 12                          |
   | · ASN-first-table origin in control register 14                       |
   | · ASN-second-table origin in ASN-first-table entry                    |
 | | · Authority-table origin in ASN-second-table entry, except when used  |
 | |   by access-register translation                                      |
   | · Linkage-table origin in control register 5 or primary ASN-second-   |
   |   table entry¹                                                        |
   | · Entry-table origin in linkage-table entry                           |
   | · Dispatchable-unit-control-table origin in control register 2        |
   | · Primary-ASN-second-table-entry origin in control register 5¹        |
 | | · Base-ASN-second-table-entry origin and subspace-ASN-second-table-   |
 | |   entry origin in dispatchable-unit control table                     |
   | · ASN-second-table-entry address in entry-table entry and access-list |
   |   entry                                                               |
   |                                                                       |
   | Permanently Assigned Real Addresses                                   |
   |                                                                       |
   | · Address of the doubleword into which TEST PENDING INTERRUPTION      |
   |   stores when the second-operand address is zero                      |
   | · Addresses of PSWs, interruption codes, and the associated informa-  |
   |   tion used during interruption                                       |
   | · Addresses used for machine-check logout and save areas              |
   |                                                                       |
   | Addresses Which Are Unpredictably Real or Absolute                    |
   |                                                                       |
   | · Segment-table origin in control registers 1, 7, and 13 and in       |
   |   access-register-specified segment-table designation                 |
   | · Page-table origin in segment-table entry                            |
   | · Address of segment-table entry or page-table entry provided by LOAD |
   |   REAL ADDRESS                                                        |
 | | · The dispatchable-unit or primary-space access-list origin and the   |
 | |   authority-table origin (in the ASTE designated by the ALE used) used|
 | |   by access-register translation                                      |
   |_______________________________________________________________________|
    _______________________________________________________________________ 
   | Absolute Addresses                                                    |
   |                                                                       |
   | · Prefix value                                                        |
   | · Channel-program address in ORB                                      |
   | · Data address in CCW                                                 |
   | · IDAW address in a CCW specifying indirect data addressing           |
   | · CCW address in a CCW specifying transfer in channel                 |
   | · Data address in IDAW                                                |
   | · Measurement-block origin specified in SET CHANNEL MONITOR           |
   | · Address limit specified in SET ADDRESS LIMIT                        |
   | · Addresses used by the store-status-at-address SIGNAL PROCESSOR order|
   | · Failing-storage address stored in the word at real location 248     |
   | · CCW address in SCSW                                                 |
   |                                                                       |
   | Permanently Assigned Absolute Addresses                               |
   |                                                                       |
   | · Addresses used for the store-status function                        |
   | · Addresses of PSW and first two CCWs used for initial program loading|
   |                                                                       |
   | Addresses Not Used to Reference Storage                               |
   |                                                                       |
   | · PER starting address in control register 10                         |
   | · PER ending address in control register 11                           |
   | · Address stored in the word at real location 156 for a monitor event |
   | · Address in shift instructions and other instructions specified not  |
   |   to use the address to reference storage                             |
   |_______________________________________________________________________|
   |Explanation:                                                           |
   |                                                                       |
   | ¹ When the address-space-function (ASF) control, bit 15 of control    |
   |   register 0, is zero, control register 5 contains the linkage-table  |
   |   origin.  When the ASF control is one, control register 5 contains   |
   |   the primary-ASN-second-table-entry origin, and the linkage-table    |
   |   origin is in the primary ASN-second-table entry.                    |
   |_______________________________________________________________________|

   Figure  3-11. Handling of Addresses

   Figure 3-12  shows  the  format  and  extent  of the assigned locations in
   storage.  The locations are used as follows.

0-7

(Absolute Address)

Initial-Program-Loading PSW: The first eight bytes read during the initial-program-loading (IPL) initial-read operation are stored at locations 0-7. The contents of these locations are used as the new PSW at the completion of the IPL operation. These locations may also be used for temporary storage at the initiation of the IPL operation.

0-7

(Real Address)

Restart New PSW: The new PSW is fetched from locations 0-7 during a restart interruption.

8-15

(Absolute Address)

Initial-Program-Loading CCW1: Bytes 8-15 read during the initial-program-loading (IPL) initial-read operation are stored at locations 8-15. The contents of these locations are ordinarily used as the next CCW in an IPL CCW chain after completion of the IPL initial-read operation.

8-15

(Real Address)

Restart Old PSW: The current PSW is stored as the old PSW at locations 8-15 during a restart interruption.

16-23

(Absolute Address)

Initial-Program-Loading CCW2: Bytes 16-23 read during the initial-program loading (IPL) initial-read operation are stored at locations 16-23. The contents of these locations may be used as another CCW in the IPL CCW chain to follow IPL CCW1.

24-31

(Real Address)

External Old PSW: The current PSW is stored as the old PSW at locations 24-31 during an external interruption.

32-39

(Real Address)

Supervisor-Call Old PSW: The current PSW is stored as the old PSW at locations 32-39 during a supervisor-call interruption.

40-47

(Real Address)

Program Old PSW: The current PSW is stored as the old PSW at locations 40-47 during a program interruption.

48-55

(Real Address)

Machine-Check Old PSW: The current PSW is stored as the old PSW at locations 48-55 during a machine-check interruption.

56-63

(Real Address)

Input/Output Old PSW: The current PSW is stored as the old PSW at locations 56-63 during an I/O interruption.

88-95

(Real Address)

External New PSW: The new PSW is fetched from locations 88-95 during an external interruption.

96-103

(Real Address)

Supervisor-Call New PSW: The new PSW is fetched from locations 96-103 during a supervisor-call interruption.

104-111

(Real Address)

Program New PSW: The new PSW is fetched from locations 104-111 during a program interruption.

112-119

(Real Address)

Machine-Check New PSW: The new PSW is fetched from locations 112-119 during a machine-check interruption.

120-127

(Real Address)

Input/Output New PSW: The new PSW is fetched from locations 120-127 during an I/O interruption.

128-131

(Real Address)

External-Interruption Parameter: During an external interruption due to service signal, the parameter associated with the interruption is stored at locations 128-131.

132-133

(Real Address)

CPU Address: During an external interruption due to malfunction alert, emergency signal, or external call, the CPU address associated with the source of the interruption is stored at locations 132-133. For all other external-interruption conditions, zeros are stored at locations 132-133.

134-135

(Real Address)

External-Interruption Code: During an external interruption, the interruption code is stored at locations 134-135.

136-139

(Real Address)

Supervisor-Call-Interruption Identification: During a supervisor-call interruption, the instruction-length code is stored in bit positions 5 and 6 of location 137, and the interruption code is stored at locations 138-139. Zeros are stored at location 136 and in the remaining bit positions of location 137.

140-143

(Real Address)

Program-Interruption Identification: During a program interruption, the instruction-length code is stored in bit positions 5 and 6 of location 141, and the interruption code is stored at locations 142-143. Zeros are stored at location 140 and in the remaining bit positions of location 141.

144-147

(Real Address)

Translation-Exception Identification: During a program interruption due to a segment-translation exception or a page-translation exception, the segment-index and page-index portion of the virtual address causing the exception is stored at locations 144-147. This address is sometimes referred to as the translation-exception address. Bits 20-29 of the address are unpredictable. Bits 30-31 of the address are set to identify the segment-table designation (STD) used in the translation, as follows:

         Bit     Bit
         30      31      Meaning
            0       0    Primary STD was used.
            0       1    CPU  was in the access-register mode, and either the
                         access  was  an  instruction  fetch  or  it  was   a
                         storage-operand  reference that used an AR-specified
                         STD (the access was not an implicit reference to the
                         linkage stack).    The  exception  access  id,  real
                         location  160,  can be examined to determine the STD
                         used.  However, if the primary, secondary,  or  home
                         STD  was  used, bits 30 and 31 may be set to 00, 10,
                         or 11, respectively, instead of to 01.
            1       0    Secondary STD was used.
            1       1    Home STD was used (includes the case of an  implicit
                         reference to the linkage stack).

The CPU may avoid setting bits 30 and 31 to 01 by recognizing that the access was an instruction fetch, that access-list-entry token 00000000 or 00000001 hex was used, or that the access-list-entry token designated, through an access-list entry, an ASN-second-table entry containing an STD equal to the primary STD, secondary STD, or home STD.

Bit 0 of location 144 is set to one if the CPU was in either the primary-space mode or the secondary-space mode and the secondary STD was used; otherwise, bit 0 is set to zero.

During a program interruption due to an AFX-translation, ASX-translation, primary-authority, or secondary-authority exception, the ASN being translated is stored at locations 146-147. Zeros are stored at locations 144-145.

During a program interruption due to a space-switch event, an identification of the old instruction space is stored at locations 146-147, and the old instruction-space space-switch-event-control bit is placed in bit position 0 and zeros are placed in bit positions 1-15 of locations 144-145. The identification and bit stored are as follows:

• If the CPU was in the primary-space, secondary-space, or access-register mode before the operation, the old PASN, bits 16-31 of control register 4 before the operation, is stored at locations 146-147, and the old primary space-switch-event-control bit, bit 0 of control register 1 before the operation, is placed in bit position 0 of locations 144-145.

• If the CPU was in the home-space mode before the operation, zeros are stored at locations 146-147, and the home space-switch-event-control bit, bit 0 of control register 13, is placed in bit position 0 of locations 144-145.

During a program interruption due to an LX-translation or EX-translation exception, the PC number is stored in bit positions 12-31 of the word at locations 144-147. Bits 0-11 are set to zeros.

If the suppression-on-protection facility is installed, then, during a program interruption due to a protection exception, information is stored at locations 144-147 as described in "Suppression on Protection" in topic 3.4.5.

148-149

(Real Address)

Monitor-Class Number: During a program interruption due to a monitor event, the monitor-class number is stored at location 149, and zeros are stored at location 148.

150-151

(Real Address)

PER Code: During a program interruption due to a PER event with PER 1, the PER code is stored in bit positions 0-3 of locations 150-151, and zeros are stored in bit positions 4-15. With PER 2, the PER code is stored in bit positions 0-2 and 4 of locations 150-151, and other information is or may be stored as described in "Identification of Cause" in topic 4.5.2.1.

152-155

(Real Address)

PER Address: During a program interruption due to a PER event, the PER address is stored at locations 152-155. Bit 0 of location 152 is set to zero.

156-159

(Real Address)

Monitor Code: During a program interruption due to a monitor event, the monitor code is stored at locations 156-159.

160

(Real Address)

Exception Access Identification: During a program interruption due to a segment-translation exception or a page-translation exception, an indication of the address space to which the exception applies may be stored at location 160. If the CPU was in the access-register mode and the access was an instruction fetch, including a fetch of the target of an EXECUTE instruction, zeros are stored at location 160. If the CPU was in the access-register mode and the access was a storage-operand reference that used an AR-specified segment-table designation, the number of the access register used is stored in bit positions 4-7 of location 160, and zeros are stored in bit positions 0-3. (In either of the two cases described so far, storing at location 160 occurs regardless of the value stored in bit positions 30 and 31 of real locations 144-147.) If the CPU was in the access-register mode but the access was an implicit reference to the linkage stack, or if the CPU was not in the access-register mode, the contents of location 160 are unpredictable.

During a program interruption due to an ALEN-translation, ALE-sequence, ASTE-validity, ASTE-sequence, or extended-authority exception recognized during access-register translation, the number of the access register used is stored in bit positions 4-7 of location 160, and zeros are stored in bit positions 0-3. During a program interruption due to an ASTE-validity or ASTE-sequence exception recognized during a subspace-replacement operation, all zeros are stored at location 160.

If the suppression-on-protection facility is installed, then, during a program interruption due to a protection exception, information is stored at location 160 as described in "Suppression on Protection" in topic 3.4.5.

161

(Real Address)

PER Access Identification: During a program interruption due to a PER storage-alteration event, an indication of the address space to which the event applies may be stored at location 161. If the access used an AR-specified segment-table designation, the number of the access register used is stored in bit positions 4-7 of location 161, and zeros are stored in bit positions 0-3. However, with PER 1, the contents of location 161 are unpredictable if the instruction that caused the event turned DAT off. Also, with PER 1 or PER 2, the contents of location 161 are unpredictable if (1) the CPU was in the access-register mode but the access was an implicit reference to the linkage stack, (2) the CPU was not in the access-register mode, or (3) bit 2 of the PER code is one but indicates a store-using-real-address event instead of a storage-alteration event.

184-187

(Real Address)

Subsystem-Identification Word: During an I/O interruption, the subsystem-identification word is stored at locations 184-187.

188-191

(Real Address)

I/O-Interruption Parameter: During an I/O interruption, the interruption parameter from the associated subchannel is stored at locations 188-191.

216-223

(Absolute Address)

Store-Status CPU-Timer Save Area: During the execution of the store-status operation, the contents of the CPU timer are stored at locations 216-223.

216-223

(Real Address)

Machine-Check CPU-Timer Save Area: During a machine-check interruption, the contents of the CPU timer are stored at locations 216-223.

224-231

(Absolute Address)

Store-Status Clock-Comparator Save Area: During the execution of the store-status operation, the contents of the clock comparator are stored at locations 224-231.

224-231

(Real Address)

Machine-Check Clock-Comparator Save Area: During a machine-check interruption, the contents of the clock comparator are stored at locations 224-231.

232-239

(Real Address)

Machine-Check-Interruption Code: During a machine-check interruption, the machine-check-interruption code is stored at locations 232-239.

244-247

(Real Address)

External-Damage Code: During a machine-check interruption due to certain external-damage conditions, depending on the model, an external-damage code may be stored at locations 244-247.

248-251

(Real Address)

Failing-Storage Address: During a machine-check interruption, a failing-storage address may be stored at locations 248-251. Bit 0 of location 248 is set to zero.

256-263

(Absolute Address)

Store-Status PSW Save Area: During the execution of the store-status operation, the contents of the current PSW are stored at locations 256-263.

256-271

(Real Address)

Fixed-Logout Area: Depending on the model, logout information may be stored at locations 256-271 during a machine-check interruption.

264-267

(Absolute Address)

Store-Status Prefix Save Area: During the execution of the store-status operation, the contents of the prefix register are stored at locations 264-267.

288-351

(Absolute Address)

Store-Status Access-Register Save Area: During the execution of the store-status operation, the contents of the access registers are stored at locations 288-351.

288-351

(Real Address)

Machine-Check Access-Register Save Area: During a machine-check interruption, the contents of the access registers are stored at locations 288-351.

352-383

(Absolute Address)

Store-Status Floating-Point-Register Save Area: During the execution of the store-status operation, the contents of the floating-point registers are stored at locations 352-383.

352-383

(Real Address)

Machine-Check Floating-Point-Register Save Area: During a machine-check interruption, the contents of the floating-point registers are stored at locations 352-383.

384-447

(Absolute Address)

Store-Status General-Register Save Area: During the execution of the store-status operation, the contents of the general registers are stored at locations 384-447.

384-447

(Real Address)

Machine-Check General-Register Save Area: During a machine-check interruption, the contents of the general registers are stored at locations 384-447.

448-511

(Absolute Address)

Store-Status Control-Register Save Area: During the execution of the store-status operation, the contents of the control registers are stored at locations 448-511.

448-511

(Real Address)

Machine-Check Control-Register Save Area: During a machine-check interruption, the contents of the control registers are stored at locations 448-511.

     Hex  Dec
   __________ _______________________________________________________________ 
      0    0 | Initial-Program-Loading PSW; or Restart New PSW               |
             |                                                               |
      4    4 |                                                               |
   __________|_______________________________________________________________|
      8    8 | Initial-Program-Loading CCW1; or Restart Old PSW              |
             |                                                               |
      C   12 |                                                               |
   __________|_______________________________________________________________|
     10   16 | Initial-Program Loading CCW2                                  |
             |                                                               |
     14   20 |                                                               |
   __________|_______________________________________________________________|
     18   24 | External Old PSW                                              |
             |                                                               |
     1C   28 |                                                               |
   __________|_______________________________________________________________|
     20   32 | Supervisor-Call Old PSW                                       |
             |                                                               |
     24   36 |                                                               |
   __________|_______________________________________________________________|
     28   40 | Program Old PSW                                               |
             |                                                               |
     2C   44 |                                                               |
   __________|_______________________________________________________________|
     30   48 | Machine-Check Old PSW                                         |
             |                                                               |
     34   52 |                                                               |
   __________|_______________________________________________________________|
     38   56 | Input/Output Old PSW                                          |
             |                                                               |
     3C   60 |                                                               |
   __________|_______________________________________________________________|
     40   64 |                                                               |
             |                                                               |
     44   68 |                                                               |
             |                                                               |
     48   72 |                                                               |
             |                                                               |
     4C   76 |                                                               |
             |                                                               |
     50   80 |                                                               |
             |                                                               |
     54   84 |                                                               |
   __________|_______________________________________________________________|
     58   88 | External New PSW                                              |
             |                                                               |
     5C   92 |                                                               |
   __________|_______________________________________________________________|
     60   96 | Supervisor-Call New PSW                                       |
             |                                                               |
     64  100 |                                                               |
   __________|_______________________________________________________________|
     68  104 | Program New PSW                                               |
             |                                                               |
     6C  108 |                                                               |
   __________|_______________________________________________________________|
     70  112 | Machine-Check New PSW                                         |
             |                                                               |
     74  116 |                                                               |
   __________|_______________________________________________________________|
     78  120 | Input/Output New PSW                                          |
             |                                                               |
     7C  124 |                                                               |
   __________|_______________________________________________________________|
    Hex  Dec
   __________ _______________________________________________________________ 
     80  128 | External-Interruption Parameter                               |
   __________|_______________________________ _______________________________|
     84  132 | CPU Address                   | External-Interruption Code    |
   __________|_________________________ ___ _|_______________________________|
     88  136 |0 0 0 0 0 0 0 0 0 0 0 0 0|ILC|0| SVC-Interruption Code         |
   __________|_________________________|___|_|_______________________________|
     8C  140 |0 0 0 0 0 0 0 0 0 0 0 0 0|ILC|0| Program-Interruption Code     |
   __________|_________________________|___|_|_______________________________|
     90  144 | Translation-Exception Identification                          |
   __________|_______________________________ _______ _____ __ ______________|
     94  148 | Monitor-Class Number          |PER Cde|ATMID|SI|              |
   __________|_______________________________|_______|_____|__|______________|
     98  152 | PER Address                                                   |
   __________|_______________________________________________________________|
     9C  156 | Monitor Code                                                  |
   __________|_______________ _______________ _______________________________|
     A0  160 |Exc. Access ID | PER Access ID |                               |
   __________|_______________|_______________|_______________________________|
     A4  164 |                                                               |
             |                                                               |
     A8  168 |                                                               |
             |                                                               |
     AC  172 |                                                               |
             |                                                               |
     B0  176 |                                                               |
             |                                                               |
     B4  180 |                                                               |
   __________|_______________________________________________________________|
     B8  184 | Subsystem-Identification Word                                 |
   __________|_______________________________________________________________|
     BC  188 | I/O-Interruption Parameter                                    |
   __________|_______________________________________________________________|
     C0  192 |                                                               |
             |                                                               |
     C4  196 |                                                               |
             |                                                               |
     C8  200 |                                                               |
             |                                                               |
     CC  204 |                                                               |
             |                                                               |
     D0  208 |                                                               |
             |                                                               |
     D4  212 |                                                               |
   __________|_______________________________________________________________|
     D8  216 | Store-Status CPU-Timer Save Area; or Machine-Check CPU-Timer  |
             |   Save Area                                                   |
     DC  220 |                                                               |
   __________|_______________________________________________________________|
     E0  224 | Store-Status Clock-Comparator Save Area; or Machine-Check     |
             |   Clock-Comparator Save Area                                  |
     E4  228 |                                                               |
   __________|_______________________________________________________________|
     E8  232 | Machine-Check Interruption Code                               |
             |                                                               |
     EC  236 |                                                               |
   __________|_______________________________________________________________|
     F0  240 |                                                               |
   __________|_______________________________________________________________|
     F4  244 | External-Damage Code                                          |
   __________|_______________________________________________________________|
     F8  248 | Failing-Storage Address                                       |
   __________|_______________________________________________________________|
     FC  252 |                                                               |
   __________|_______________________________________________________________|
    Hex  Dec
   __________ _______________________________________________________________ 
    100  256 | Store-Status PSW Save Area; or Fixed-Logout Area (Part 1)     |
             |                                                               |
    104  260 |                                                               |
   __________|_______________________________________________________________|
    108  264 | Store-Status Prefix Save Area; or Fixed-Logout Area (Part 2)  |
   __________|_______________________________________________________________|
    10C  268 | Fixed-Logout Area (Part 3)                                    |
   __________|_______________________________________________________________|
    110  272 |                                                               |
             |                                                               |
             /                                                               /
             |                                                               |
    11C  284 |                                                               |
   __________|_______________________________________________________________|
    120  288 | Store-Status Access-Register Save Area; or Machine-Check      |
             |   Access-Register Save Area                                   |
    124  292 |                                                               |
             |                                                               |
    128  296 |                                                               |
             |                                                               |
    12C  300 |                                                               |
             |                                                               |
             /                                                               /
             |                                                               |
    154  340 |                                                               |
             |                                                               |
    158  344 |                                                               |
             |                                                               |
    15C  348 |                                                               |
   __________|_______________________________________________________________|
    160  352 | Store-Status Floating-Point-Register Save Area; or Machine-   |
             |   Check Floating-Point-Register Save Area                     |
    164  356 |                                                               |
             |                                                               |
    168  360 |                                                               |
             |                                                               |
    16C  364 |                                                               |
             |                                                               |
    170  368 |                                                               |
             |                                                               |
    174  372 |                                                               |
             |                                                               |
    178  376 |                                                               |
             |                                                               |
    17C  380 |                                                               |
   __________|_______________________________________________________________|
    180  384 | Store-Status General-Register Save Area; or Machine-Check     |
             |   General-Register Save Area                                  |
    184  388 |                                                               |
             |                                                               |
    188  392 |                                                               |
             |                                                               |
    18C  396 |                                                               |
             |                                                               |
             /                                                               /
             |                                                               |
    1B4  436 |                                                               |
             |                                                               |
    1B8  440 |                                                               |
             |                                                               |
    1BC  444 |                                                               |
   __________|_______________________________________________________________|
    Hex  Dec
   __________ _______________________________________________________________ 
    1C0  448 | Store-Status Control-Register Save Area; or Machine-Check     |
             |   Control-Register Save Area                                  |
    1C4  452 |                                                               |
             |                                                               |
    1C8  456 |                                                               |
             |                                                               |
    1CC  460 |                                                               |
             |                                                               |
             /                                                               /
             |                                                               |
    1F4  500 |                                                               |
             |                                                               |
    1F8  504 |                                                               |
             |                                                               |
    1FC  508 |                                                               |
   __________|_______________________________________________________________|

   Figure  3-12. Assigned Storage Locations

   This   chapter   describes  in  detail  the  facilities  for  controlling,
   measuring, and recording the operation of one or more CPUs.

Subtopics:

• 4.1 Stopped, Operating, Load, and Check-Stop States
• 4.2 Program-Status Word
• 4.3 Control Registers
• 4.4 Tracing
• 4.5 Program-Event Recording
• 4.6 Timing
• 4.7 Externally Initiated Functions
• 4.8 Multiprocessing
• 4.9 CPU Signaling and Response

   The  stopped,  operating,  load,  and  check-stop states are four mutually
   exclusive states of the CPU.   When the  CPU  is  in  the  stopped  state,
   instructions  and  interruptions, other than the restart interruption, are
   not executed.  In the operating state, the CPU executes  instructions  and
   takes  interruptions,  subject  to  the control of the program-status word
   (PSW) and control registers, and in the manner specified by the setting of
   the operator-facility rate control.  The CPU is in the load  state  during
   the  initial-program-loading  operation.    The  CPU enters the check-stop
   state only as the result of machine malfunctions.

Subtopics:

• 4.1.1 Stopped State
• 4.1.2 Operating State
• 4.1.3 Load State
• 4.1.4 Check-Stop State

   The  CPU changes from the operating state to the stopped state by means of
   the stop function.  The stop function is performed when:

• The stop key is activated while the CPU is in the operating state.

• The CPU accepts a stop or stop-and-store-status order specified by a SIGNAL PROCESSOR instruction addressed to this CPU while it is in the operating state.

• The CPU has finished the execution of a unit of operation initiated by performing the start function with the rate control set to the instruction-step position.

Before entering the stopped state by means of the stop function, all pending allowed interruptions occur while the CPU is still in the operating state. They cause the old PSW to be stored and the new PSW to be fetched before the stopped state is entered. While the CPU is in the stopped state, interruption conditions remain pending.

• The CPU reset is completed. However, when the reset operation is performed as part of initial program loading for this CPU, then the CPU is placed in the load state and does not necessarily enter the stopped state.

• An address comparison indicates equality and stopping on the match is specified.

If the CPU is in the stopped state when an INVALIDATE PAGE TABLE ENTRY instruction is executed on another CPU in the configuration, the invalidation may be performed immediately or may be delayed until the CPU leaves the stopped state.

   The  CPU changes from the stopped state to the operating state by means of
   the  start  function  or  when  a  restart  interruption  (see  Chapter 6,
   "Interruptions") occurs.

   The  CPU  enters  the load state when the load-normal or load-clear key is
   activated.   (See "Initial Program Loading"  in  topic 4.7.2.    See  also
   "Initial     Program     Loading"    in    topic 17.3.1.)        If    the
   initial-program-loading  operation  is  completed  successfully,  the  CPU
   changes  from  the  load  state  to the operating state, provided the rate
   control is set to the process position; if the rate control is set to  the
   instruction-step  position,  the  CPU  changes  from the load state to the
   stopped state.

   The  check-stop  state,  which  the CPU enters on certain types of machine
   malfunction, is described in Chapter 11, "Machine-Check Handling." The CPU
   leaves the check-stop state when CPU reset is performed.

   Programming Notes:

   The  current  program-status  word  (PSW)  in the CPU contains information
   required for the execution of the currently active program.  The PSW is 64
   bits in length and includes the instruction address, condition  code,  and
   other  control fields.  In general, the PSW is used to control instruction
   sequencing and to hold and indicate much of  the  status  of  the  CPU  in
   relation  to the program currently being executed.  Additional control and
   status information is  contained  in  control  registers  and  permanently
   assigned storage locations.

    __________________________ ___________ ___________ ___________ ___________ ___________ ___________ 
   |                          |           |           |           |           | Condition |           |
   |                          |           |           |           |  Address- | Code and  |           |
   |                          |           |           |  Problem  |   Space   |  Program  |Addressing |
   |                          |System Mask|  PSW Key  |   State   |  Control  |   Mask    |   Mode    |
   |                          | (PSW Bits | (PSW Bits |   (PSW    | (PSW Bits | (PSW Bits |   (PSW    |
   |                          |   0-7)    |   8-11)   |  Bit 15)  |   16-17)  |  18-23)   |  Bit 32)  |
   |                          |_____ _____|_____ _____|_____ _____|_____ _____|_____ _____|_____ _____|
   |       Instruction        |Saved| Set |Saved| Set |Saved| Set |Saved| Set |Saved| Set |Saved| Set |
   |__________________________|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|
   |BRANCH AND LINK           | No  | No  | No  | No  | No  | No  | No  | No  | AM  | No  | AM  | No  |
   |BRANCH AND SAVE           | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  | Yes | No  |
   |BRANCH AND SAVE AND SET   | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  | Yes | Yes¹|
   |  MODE                    |     |     |     |     |     |     |     |     |     |     |     |     |
 | |BRANCH AND SET AUTHORITY  | No  | No  | Yes | Yes | Yes | Yes | No  | No  | No  | No  | Yes | Yes |
   |BRANCH AND SET MODE       | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  | Yes¹| Yes¹|
   |__________________________|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|
   |BRANCH AND STACK          | Yes | No  | Yes | No  | Yes | No  | Yes | No  | Yes | No  | Yes¹| No  |
   |BRANCH IN SUBSPACE GROUP  | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  | Yes¹| Yes |
   |INSERT PROGRAM MASK       | No  | No  | No  | No  | No  | No  | No  | No  | Yes | No  | No  | No  |
   |INSERT PSW KEY            | No  | No  | Yes | No  | No  | No  | No  | No  | No  | No  | No  | No  |
   |INSERT ADDRESS SPACE      | No  | No  | No  | No  | No  | No  | Yes | No  | No  | No  | No  | No  |
   |  CONTROL                 |     |     |     |     |     |     |     |     |     |     |     |     |
   |__________________________|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|
   |Basic PROGRAM CALL        | No  | No  | No  | No  | Yes | Yes | No  | No  | No  | No  | Yes | Yes |
   |Stacking PROGRAM CALL     | Yes | No  | Yes | PKC | Yes | Yes | Yes | Yes | Yes | No  | Yes | Yes |
   |PROGRAM RETURN            | No  | Yes²| No  | Yes | No  | Yes | No  | Yes | No  | Yes³| No  | Yes |
   |PROGRAM TRANSFER          | No  | No  | No  | No  | No  | Yes4| No  | No  | No  | No  | No  | Yes |
   |SET ADDRESS SPACE CONTROL | No  | No  | No  | No  | No  | No  | No  | Yes | No  | No  | No  | No  |
   |__________________________|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|
   |SET PROGRAM MASK          | No  | No  | No  | No  | No  | No  | No  | No  | No  | Yes | No  | No  |
   |SET PSW KEY FROM ADDRESS  | No  | No  | No  | Yes | No  | No  | No  | No  | No  | No  | No  | No  |
   |SET SYSTEM MASK           | No  | Yes | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  |
   |STORE THEN AND SYSTEM MASK| Yes | ANDs| No  | No  | No  | No  | No  | No  | No  | No  | No  | No  |
   |STORE THEN OR SYSTEM MASK | Yes | ORs | No  | No  | No  | No  | No  | No  | No  | No  | No  | No  |
   |__________________________|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|_____|
   |Explanation:                                                                                      |
   |                                                                                                  |
   | ¹     The action takes place only if the associated R field in the instruction is nonzero.       |
   |                                                                                                  |
   | ²     PROGRAM RETURN does not change the PER mask.                                               |
   |                                                                                                  |
   | ³     The condition code set by PROGRAM RETURN is unpredictable.                                 |
   |                                                                                                  |
   | 4     PROGRAM TRANSFER does not change the problem-state bit from one to zero.                   |
   |                                                                                                  |
   | AM    The action depends on the addressing mode, bit 32 of the current PSW.  In the 24-bit       |
   |       addressing mode, the condition code and program mask are saved in the leftmost byte of     |
   |       the general register.  In the 31-bit addressing mode, the addressing mode, along with      |
   |       bits 1-7 of the 31-bit address, replace the leftmost byte of the register.                 |
   |                                                                                                  |
   | ANDs  The logical AND of the immediate field in the instruction and the current system mask      |
   |       replaces the current system mask.                                                          |
   |                                                                                                  |
   | ORs   The logical OR of the immediate field in the instruction and the current system mask       |
   |       replaces the current system mask.                                                          |
   |                                                                                                  |
   | PKC   When the PSW-key-control bit, bit 131 of the 32-byte entry-table entry, is zero, the PSW   |
   |       key remains unchanged.  When the PSW-key-control bit is one, the PSW key is set with the   |
   |       entry key, bits 136-139 of the entry-table entry.                                          |
   |__________________________________________________________________________________________________|

   Figure  4-1. Operations on PSW Fields

Subtopics:

• 4.2.1 Program-Status-Word Format

    _ _ _____ _ _ _ _____ _ _ _ _ ___ ___ ______ _______________ 
   | | |     | |I|E|     | | | | |   |   | Prog |               |
   |0|R|0 0 0|T|O|X| Key |1|M|W|P|A S|C C| Mask |0 0 0 0 0 0 0 0|
   |_|_|_____|_|_|_|_____|_|_|_|_|___|___|______|_______________|
   0          5     8    12      16  18  20     24             31

    _ __________________________________________________________ 
   | |                                                          |
   |A|                Instruction Address                       |
   |_|__________________________________________________________|
   32                                                          63

   Figure  4-2. PSW Format

   The  following  is  a  summary  of  the functions of the PSW fields.  (See
   Figure 4-2.)

    ____________ ________________________ 
   |  Program-  |                        |
   |  Mask Bit  |    Program Exception   |
   |____________|________________________|
   |     20     |  Fixed-point overflow  |
   |     21     |  Decimal overflow      |
   |     22     |  Exponent underflow    |
   |     23     |  Significance          |
   |____________|________________________|

   When the mask bit is one, the exception results in an interruption.   When
   the  mask  bit  is  zero,  no  interruption  occurs.    The setting of the
   exponent-underflow-mask bit or the significance-mask bit  also  determines
   the  manner  in  which  the  operation is completed when the corresponding
   exception occurs.

   The  control  registers  provide  for maintaining and manipulating control
   information outside the PSW.  There are sixteen 32-bit control registers.

   Programming Notes:

    ____ _____ ___________________________________ ___________________________ _______ 
   |Ctrl|     |                                   |                           |Initial|
   |Reg |Bits |          Name of Field            |      Associated with      | Value |
   |____|_____|___________________________________|___________________________|_______|
   |  0 |  1  |SSM-suppression control            |SET SYSTEM MASK            |   0   |
   |  0 |  2  |TOD-clock-sync control             |TOD clock                  |   0   |
   |  0 |  3  |Low-address-protection control     |Low-address protection     |   0   |
   |  0 |  4  |Extraction-authority control       |Instruction authorization  |   0   |
   |  0 |  5  |Secondary-space control            |Instruction authorization  |   0   |
   |  0 |  6  |Fetch-protection-override control  |Key-controlled protection  |   0   |
   |  0 |  7  |Storage-protection-override control|Key-controlled protection  |   0   |
   |  0 | 8-12|Translation format                 |Dynamic address translation|   0   |
   |  0 | 14  |Vector control¹                    |Vector operations          |   0   |
   |  0 | 15  |Address-space-function control     |Instruction authorization  |   0   |
   |  0 | 16  |Malfunction-alert subclass mask    |External interruptions     |   0   |
   |  0 | 17  |Emergency-signal subclass mask     |External interruptions     |   0   |
   |  0 | 18  |External-call subclass mask        |External interruptions     |   0   |
   |  0 | 19  |TOD-clock sync-check subclass mask |External interruptions     |   0   |
   |  0 | 20  |Clock-comparator subclass mask     |External interruptions     |   0   |
   |  0 | 21  |CPU-timer subclass mask            |External interruptions     |   0   |
   |  0 | 22  |Service-signal subclass mask       |External interruptions     |   0   |
   |  0 | 24  |Unused²                            |                           |   1   |
   |  0 | 25  |Interrupt-key subclass mask        |External interruptions     |   1   |
   |  0 | 26  |Unused²                            |                           |   1   |
   |____|_____|___________________________________|___________________________|_______|
   |  1 |  0  |Primary space-switch-event control |Program interruptions      |   0   |
   |  1 | 1-19|Primary segment-table origin       |Dynamic address translation|   0   |
   |  1 | 22  |Primary subspace-group control     |Subspace groups            |   0   |
   |  1 | 23  |Primary private-space control      |Dynamic address translation|   0   |
   |  1 | 24  |Primary storage-alteration-event   |Program-event rec. 2 only  |   0   |
   |    |     |  control                          |                           |       |
   |  1 |25-31|Primary segment-table length       |Dynamic address translation|   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  2 | 1-25|Dispatchable-unit-control-table    |Access-register translation|   0   |
   |    |     |  origin                           |                           |       |
   |____|_____|___________________________________|___________________________|_______|
   |  3 | 0-15|PSW-key mask                       |Instruction authorization  |   0   |
   |  3 |16-31|Secondary ASN                      |Address spaces             |   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  4 | 0-15|Authorization index                |Instruction authorization  |   0   |
   |  4 |16-31|Primary ASN                        |Address spaces             |   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  5 |  0  |Subsystem-linkage control³         |Instruction authorization  |   0   |
   |  5 | 1-24|Linkage-table origin³              |PC-number translation      |   0   |
   |  5 |25-31|Linkage-table length³              |PC-number translation      |   0   |
   |  5 | 1-25|Primary-ASN-second-table-entry     |Access-register translation|   0   |
   |    |     |  origin4                          |                           |       |
   |____|_____|___________________________________|___________________________|_______|
    ____ _____ ___________________________________ ___________________________ _______ 
   |Ctrl|     |                                   |                           |Initial|
   |Reg |Bits |          Name of Field            |      Associated with      | Value |
   |____|_____|___________________________________|___________________________|_______|
   |  6 | 0-7 |I/O-interruption subclass mask     |I/O interruptions          |   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  7 | 1-19|Secondary segment-table origin     |Dynamic address translation|   0   |
   |  7 | 22  |Secondary subspace-group control   |Subspace groups            |   0   |
   |  7 | 23  |Secondary private-space control    |Dynamic address translation|   0   |
   |  7 | 24  |Secondary storage-alteration-event |Program-event rec. 2 only  |   0   |
   |    |     |  control                          |                           |       |
   |  7 |25-31|Secondary segment-table length     |Dynamic address translation|   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  8 | 0-15|Extended authorization index       |Access-register translation|   0   |
   |  8 |16-31|Monitor masks                      |MONITOR CALL               |   0   |
   |____|_____|___________________________________|___________________________|_______|
   |  9 |  0  |Successful-branching-event mask    |Program-event recording    |   0   |
   |  9 |  1  |Instruction-fetching-event mask    |Program-event recording    |   0   |
   |  9 |  2  |Storage-alteration-event mask      |Program-event recording    |   0   |
   |  9 |  3  |GR-alteration-event mask           |Program-event rec. 1 only  |   0   |
   |  9 |  4  |Store-using-real-address-event mask|Program-event recording    |   0   |
   |  9 |  8  |Branch-address control             |Program-event rec. 2 only  |   0   |
   |  9 | 10  |Storage-alteration-space control   |Program-event rec. 2 only  |   0   |
   |  9 |16-31|PER general-register masks         |Program-event rec. 1 only  |   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 10 | 1-31|PER starting address               |Program-event recording    |   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 11 | 1-31|PER ending address                 |Program-event recording    |   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 12 |  0  |Branch-trace control               |Tracing                    |   0   |
   | 12 | 1-29|Trace-entry address                |Tracing                    |   0   |
   | 12 | 30  |ASN-trace control                  |Tracing                    |   0   |
   | 12 | 31  |Explicit-trace control             |Tracing                    |   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 13 |  0  |Home space-switch-event control    |Program interruptions      |   0   |
   | 13 | 1-19|Home segment-table origin          |Dynamic address translation|   0   |
   | 13 | 22  |Ignored                            |                           |   0   |
   | 13 | 23  |Home private-space control         |Dynamic address translation|   0   |
   | 13 | 24  |Home storage-alteration-event      |Program-event rec. 2 only  |   0   |
   |    |     |  control                          |                           |       |
   | 13 |25-31|Home segment-table length          |Dynamic address translation|   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 14 |  0  |Unused²                            |                           |   1   |
   | 14 |  1  |Unused²                            |                           |   1   |
   | 14 |  3  |Channel-report-pending subclass    |I/O machine-check handling |   0   |
   |    |     |  mask                             |                           |       |
   | 14 |  4  |Recovery subclass mask             |Machine-check handling     |   0   |
   | 14 |  5  |Degradation subclass mask          |Machine-check handling     |   0   |
   | 14 |  6  |External-damage subclass mask      |Machine-check handling     |   1   |
   | 14 |  7  |Warning subclass mask              |Machine-check handling     |   0   |
   | 14 | 12  |ASN-translation control            |Instruction authorization  |   0   |
   | 14 |13-31|ASN-first-table origin             |ASN translation            |   0   |
   |____|_____|___________________________________|___________________________|_______|
   | 15 | 1-28|Linkage-stack-entry address        |Linkage-stack operations   |   0   |
   |____|_____|___________________________________|___________________________|_______|
    __________________________________________________________________________________ 
   |Explanation:                                                                      |
   |                                                                                  |
   |  The fields not listed are unassigned.  The initial value for all unlisted       |
   |  control-register positions is zero.                                             |
   |                                                                                  |
   |  ¹  Bit 14 of control register 0, the vector-control bit, is described in the    |
   |     publication IBM Enterprise Systems Architecture/390 Vector Operations,       |
   |     SA22-7207.                                                                   |
   |                                                                                  |
   |  ²  This bit is not used but is initialized to one for consistency with the      |
   |     System/370 definition.                                                       |
   |                                                                                  |
   |  ³  When the address-space-function control in control register 0 is zero,       |
   |     LOAD ADDRESS SPACE PARAMETERS, PROGRAM CALL, and PROGRAM TRANSFER treat      |
   |     control register 5 as containing the linkage-table designation (LTD)         |
   |     (subsystem-linkage control, linkage-table origin, and linkage-table length). |
   |                                                                                  |
   |  4  When the address-space-function control is one, control register 5 is        |
   |     treated as containing the primary-ASN-second-table-entry (PASTE) origin,     |
   |     and PROGRAM CALL and PROGRAM TRANSFER obtain the LTD from the PASTE.         |
   |__________________________________________________________________________________|

   Figure  4-3. Assignment of Control-Register Fields

   Tracing  assists  in  the determination of system problems by providing an
   ongoing record in storage of significant  events.    Tracing  consists  of
   three  separately controllable functions which cause entries to be made in
   a trace table:  branch tracing, ASN tracing, and explicit tracing.  Branch
   tracing and ASN tracing together are referred to as implicit tracing.

• BRANCH AND LINK (BALR only) when the R2 field is not zero
• BRANCH AND SAVE (BASR only) when the R2 field is not zero
• BRANCH AND SAVE AND SET MODE when the R2 field is not zero
• | BRANCH AND SET AUTHORITY
• BRANCH AND STACK when the R2 field is not zero
• BRANCH IN SUBSPACE GROUP

• BRANCH IN SUBSPACE GROUP
• PROGRAM CALL
• PROGRAM RETURN
• PROGRAM TRANSFER
• SET SECONDARY ASN

When explicit tracing is on, execution of TRACE causes an entry to be made in the trace table. This entry includes bits 16-63 from the TOD clock, the second operand of the TRACE instruction, and the contents of a range of general registers.

Subtopics:

• 4.4.1 Control-Register Allocation
• 4.4.2 Trace Entries
• 4.4.3 Operation

   The information to control tracing is contained in control register 12 and
   has the following format:

    _ _____________________________ _ _ 
   |B|     Trace-Entry Address     |A|E|
   |_|_____________________________|_|_|
   0  1                            30 31

    Trace entries are of eight types, as shown in Figure 4-4.

   31-Bit Branch
    _ ________________________________ 
   |1|         Branch Address         |
   |_|________________________________|
   0  1                              31


   24-Bit Branch
    ________ _________________________ 
   |00000000|     Branch Address      |
   |________|_________________________|
   0         8                       31


   BRANCH IN SUBSPACE GROUP (if ASN Tracing On)
    ________ _ _______________________ _ ______________________________ 
   |01000001|P|   Bits 9-31 of ALET   |A|        Branch Address        |
   |________|_|_______________________|_|______________________________|
   0         8                        32                              63


   SET SECONDARY ASN
    ________ ________ ________________ 
   |00010000|00000000|   New SASN     |
   |________|________|________________|
   0         8       16              31


   PROGRAM CALL
    ________ ____ ____________________ _ ____________________________ _ 
   |        |PSW |                    | |                            | |
   |00100001|Key |     PC Number      |A|       Return Address       |P|
   |________|____|____________________|_|____________________________|_|
   0         8   12                   32                              63


   PROGRAM RETURN
    ________ ____ ____ _______________ _ ____________________________ _ 
   |        |PSW |    |               | |                            | |
   |00110010|Key |0000|   New PASN    |A|       Return Address       |P|
   |________|____|____|_______________|_|____________________________|_|
   0         8   12   16              32                              63

    _ ________________________________ 
   | |                                |
   |A|  Updated Instruction Address   |
   |_|________________________________|
   64                                95


   PROGRAM TRANSFER
    ________ ____ ____ _______________ ________________________________ 
   |        |PSW |    |               |                                |
   |00110001|Key |0000|   New PASN    |            R2 Before           |
   |________|____|____|_______________|________________________________|
   0         8   12   16              32                              63
   TRACE
    ____ ____ ________ ________________________________________________ 
   |0111| N  |00000000|             TOD-Clock Bits 16-63               |
   |____|____|________|________________________________________________|
   0     4    8       16                                              63

    __________________________________ ________________/_______________ 
   |       TRACE Operand              |           (R1) - (R3)          |
   |__________________________________|________________/_______________|
   64                                 96                    95 + 32(N+1)

   Figure  4-4. Trace-Entry Formats

   When  an  instruction  which  is  subject  to tracing is executed, and the
   corresponding tracing  function  is  turned  on,  a  trace  entry  of  the
   appropriate format is made.  The real address of the trace entry is formed
   by appending two zero bits on the right to the value in bit positions 1-29
   of   control  register  12.    The  address  in  control  register  12  is
   subsequently increased by the size of the entry created.

   There are two versions of the program-event-recording (PER) facility.  The
   version  which is the same as PER in ESA/370 is named PER 1, and the other
   version is named PER 2. A model provides either PER 1 or PER 2.

• Execution of a successful branch instruction. PER 2 provides the option of having an event occur only when the branch-target location is within the designated storage area.
• Fetching of an instruction from the designated storage area.
• Alteration of the contents of the designated storage area. PER 2 provides the option of having an event occur only when the storage area is within designated address spaces.
• Alteration of the contents of designated general registers. This type of event can occur only with PER 1, not with PER 2.
• Execution of the STORE USING REAL ADDRESS instruction.

If a model implements ESA/390 with PER 2 and also System/370, general-register-alteration events may be omitted in System/370, depending on the model.

Subtopics:

• 4.5.1 Control-Register Allocation and Segment-Table Designation
• 4.5.2 Operation
• 4.5.3 Storage-Area Designation
• 4.5.4 PER Events
• 4.5.5 Indication of PER Events Concurrently with Other Interruption Conditions

   The  information  for  controlling PER resides in control registers 9, 10,
   and 11 and the segment-table designation.  The information in the  control
   registers has the following format:

   PER-1 Control Register 9
    _____ ___________ ________________ 
   | EM  |           |Gen.-Reg. Masks |
   |_____|___________|________________|
   0      5          16              31
   PER-2 Control Register 9
    _____ ____ _ _ _ ________________ 
   | EM  |    |B| |S|                |
   |_____|____|_|_|_|________________|
   0      5    8  10                31
   Control Register 10
    _ _______________________________ 
   | |       Starting Address        |
   |_|_______________________________|
   0  1                             31

   Control Register 11
    _ _______________________________ 
   | |        Ending Address         |
   |_|_______________________________|
   0  1                             31

Bit 0:

Successful-branching event

Bit 1:

Instruction-fetching event

Bit 2:

Storage-alteration event

Bit 3:

General-register-alteration event (PER 1 only)

Bit 4:

Store-using-real-address event (bit 2 must be one also)

Branch-Address Control (B): With PER 2, bit 8 of control register 9 specifies, when one, that successful-branching events occur only for branches that are to a location within the designated storage area. With PER 1, or with PER 2 when bit 8 is zero, successful-branching events occur regardless of the branch-target address. Bit 8 is ignored by PER 1.

   Segment-Table Designation
    _ ____________________ ___ _ _ _______ 
   | |Segment-Table Origin|   |P|S|  STL  |
   |_|____________________|___|_|_|_______|
   0  1                   20  23  25     31

   Programming Notes:

   PER  is  under  control  of  bit 1 of the PSW, the PER mask.  When the PER
   mask,    a     particular     PER-event     mask     bit,     and,     for
   general-register-alteration    events    (PER 1    only),   a   particular
   general-register mask bit are  all  ones,  the  CPU  is  enabled  for  the
   corresponding  type of event; otherwise, it is disabled.  However, the CPU
   is  enabled  for  the  store-using-real-address  event   only   when   the
   storage-alteration  mask bit and the store-using-real-address mask bit are
   both ones.

Subtopics:

• 4.5.2.1 Identification of Cause
• 4.5.2.2 Priority of Indication

   A  program interruption for PER sets bit 8 of the interruption code to one
   and places identifying information in real storage locations 150-155,  and
   in   location  161  if  the  PER  event  is  a  storage-alteration  event.
   Additional information is provided by means of the instruction address  in
   the program old PSW and the ILC.  The information stored in real locations
   150-155 and 161 has the following format:

   PER-1 Locations 150-151:
    ____ ____________ 
   |PERC|000000000000|
   |____|____________|
   0     4          15
   PER-2 Locations 150-151:
    _____ ____ _____ __ 
   |PERC |0000|ATMID|SI|
   |_____|____|_____|__|
   0      5    9   13 15

   Locations 152-155:
    _ _______________________________ 
   |0|          PER Address          |
   |_|_______________________________|
   0  1                             31
   Location 161:
    ____ ____ 
   |0000|PAID|
   |____|____|
   0     4   7

• With PER 1, when bits 2 and 4 in control register 9 are both ones, a one in bit position 2 of location 150 indicates the occurrence of either a storage-alteration event or a store-using-real-address event.

• With PER 2, a one in bit position 2 and a zero in bit position 4 of location 150 indicate a storage-alteration event, while ones in bit positions 2 and 4 indicate a store-using-real-address event.

Addressing-and-Translation-Mode Identification (ATMID): With PER 2, during a program interruption when a PER event is indicated, bits 32, 5, 16, and 17 of the PSW at the beginning of the execution of the instruction that caused the event may be stored in bit positions 10-13, respectively, of real locations 150-151. If bits 32, 5, 16, and 17 are stored, then a one bit is stored in bit position 9 of locations 150-151. If bits 32, 5, 16, and 17 are not stored, then zero bits are stored in bit positions 9-13 of locations 150-151.

Bit Meaning

9

ATMID-validity bit

10

PSW bit 32

11

PSW bit 5

12

PSW bit 16

13

PSW bit 17

• BRANCH AND SAVE AND SET MODE (BASSM)
• | BRANCH AND SET AUTHORITY (BSA)
• BRANCH AND SET MODE (BSM)
• BRANCH IN SUBSPACE GROUP (BSG)
• LOAD PSW (LPSW)
• PROGRAM CALL (PC)
• PROGRAM RETURN (PR)
• PROGRAM TRANSFER (PT)
• SET ADDRESS SPACE CONTROL (SAC)
• SET ADDRESS SPACE CONTROL FAST (SACF)
• SET SYSTEM MASK (SSM)
• STORE THEN AND SYSTEM MASK (STNSM)
• STORE THEN OR SYSTEM MASK (STOSM)
• SUPERVISOR CALL (SVC)

In the case of an instruction-fetching PER event caused by SET ADDRESS SPACE CONTROL or SET ADDRESS SPACE CONTROL FAST, bits 12 and 13 of the ATMID, which correspond to bits 16 and 17 of the PSW, may indicate that the CPU was in the primary-space mode when it actually was in the primary-space, secondary-space, or access-register mode. In any of those modes, the instruction fetch is from the primary address space.

Bits 14-15 Meaning

00

Primary STD was used.

01

An AR-specified STD was used. The PER access id, real location 161, can be examined to determine the STD used. However, if the primary, secondary, or home STD was used, bits 14 and 15 may be set to 00, 10, or 11, respectively, instead of to 01.

10

Secondary STD was used.

11

Home STD was used.

If a storage-alteration event is not indicated in the PER code (bit 2 is zero or bit 4 is one) or DAT was off, zeros are stored in bit positions 14 and 15.

   Programming Notes:

   When  a  program  interruption occurs and more than one PER event has been
   recognized, all recognized PER events are concurrently  indicated  in  the
   PER   code.    Additionally,  if  another  program-interruption  condition
   concurrently exists, the interruption code for  the  program  interruption
   indicates both the PER condition and the other condition.

1. When the instruction is due to be interrupted for an asynchronous condition (I/O, external, restart, or repressible machine-check condition), a program interruption for the PER event occurs first, and the other interruptions occur subsequently (subject to the mask bits in the new PSW) in the normal priority order.

2. When the stop function is performed, a program interruption indicating the PER event occurs before the CPU enters the stopped state.

3. When any program exception is recognized, PER events recognized for that instruction execution are indicated concurrently.

4. Depending on the model, in certain situations, recognition of a PER event may appear to cause the instruction to be interrupted prematurely without concurrent indication of a program exception, without an interruption for any asynchronous condition, or without the CPU entering the stopped state.

Programming Notes:

1. The instructions LOAD PSW, SET SYSTEM MASK, STORE THEN AND SYSTEM MASK, and SUPERVISOR CALL can cause an instruction-fetching event and disable the CPU for PER interruptions. Additionally, STORE THEN AND SYSTEM MASK can cause a storage-alteration event to be indicated. In all these cases, the program old PSW associated with the program interruption for the PER event may indicate that the CPU was disabled for PER events.

2. An instruction-fetching event may be recognized during execution of a LOAD CONTROL instruction that changes the value of the PER-event masks in control register 9 or the addresses in control registers 10 and 11 controlling indication of instruction-fetching events.

3. In the access-register mode a storage-alteration event that is permitted by a one value of the storage-alteration-event bit in a segment-table designation in an ASN-second-table entry (designated by an access-list entry) may be caused by any store-type instruction that changes the value of the bit from one to zero.

   Two    types    of   PER   events.--instruction   fetching   and   storage
   alteration.--always involve the designation of an area in storage.    With
   PER 2,  successful-branching  events  may  involve this designation.   The
   storage area starts at the location designated by the starting address  in
   control  register  10  and  extends  up  to  and  including  the  location
   designated by the ending address in control register 11.  The area extends
   to the right of the starting address.

Subtopics:

• 4.5.4.1 Successful Branching
• 4.5.4.2 Instruction Fetching
• 4.5.4.3 Storage Alteration
• 4.5.4.4 General-Register Alteration
• 4.5.4.5 Store Using Real Address
  

   With  PER 1,  or  with  PER 2  when  the branch-address control in control
   register 9 is zero, a successful-branching event occurs independent of the
   branch-target address.  With PER 2 when the branch-address control is one,
   a successful-branching event occurs  only  when  the  first  byte  of  the
   branch-target  instruction  is fetched from the storage area designated by
   control registers 10 and 11.

• BRANCH AND LINK (BAL, BALR)
• BRANCH AND SAVE (BAS, BASR)
• BRANCH AND SAVE AND SET MODE (BASSM)
• | BRANCH AND SET AUTHORITY (BSA)
• BRANCH AND SET MODE (BSM)
• BRANCH AND STACK (BAKR)
• BRANCH IN SUBSPACE GROUP (BSG)
• BRANCH ON CONDITION (BC, BCR)
• BRANCH ON COUNT (BCT, BCTR)
• BRANCH ON INDEX HIGH (BXH)
• BRANCH ON INDEX LOW OR EQUAL (BXLE)
• BRANCH RELATIVE AND SAVE (BRAS)
• BRANCH RELATIVE ON CONDITION (BRC)
• BRANCH RELATIVE ON COUNT (BRCT)
• BRANCH RELATIVE ON INDEX HIGH (BRXH)
• BRANCH RELATIVE ON INDEX LOW OR EQUAL (BRXLE)

• PROGRAM CALL (PC)
• PROGRAM RETURN (PR)
• PROGRAM TRANSFER (PT)

A successful-branching event causes a PER successful-branching event to be recognized if bit 0 of the PER-event masks is one and the PER mask in the PSW is one.

   An  instruction-fetching event occurs if the first byte of the instruction
   is within the storage area designated by control registers 10 and 11.   An
   instruction-fetching  event also occurs if the first byte of the target of
   EXECUTE is within the designated storage area.

   A  storage-alteration  event  occurs whenever a CPU, by using a logical or
   virtual address, makes a store access without an access exception  to  the
   storage  area  designated  by  control registers 10 and 11.  However, with
   PER 2 when DAT is on and the storage-alteration-space control  in  control
   register  9  is one, the event occurs only if the storage-alteration-event
   bit is one in the  segment-table  designation  that  is  used  by  DAT  to
   translate the reference to the storage location.

   With  PER 1,  a  general-register-alteration  event  occurs  whenever  the
   contents  of   a   general   register   are   replaced.      With   PER 2,
   general-register-alteration  events  do not occur.   The remainder of this
   description applies only to PER 1.

1. Register-to-register load instructions are considered to alter the register contents even when both operand addresses designate the same register.

2. Addition or subtraction of zero and multiplication or division by one are considered to constitute alteration.

3. Logical and fixed-point shift operations are considered to alter the register contents even for shift amounts of zero.

4. The branching instructions BRANCH ON INDEX HIGH and BRANCH ON INDEX LOW OR EQUAL are considered to alter the first operand even when zero is added to its value.

   A  store-using-real-address  event  occurs  whenever  the STORE USING REAL
   ADDRESS instruction is executed.

   The  following  rules  govern  the  indication  of PER events caused by an
   instruction that also causes a  program  exception,  a  monitor  event,  a
   space-switch event, or a supervisor-call interruption.

1. The indication of an instruction-fetching event does not depend on whether the execution of the instruction was completed, terminated, suppressed, or nullified. However, when an access exception applies to the first, second, or third halfword of the instruction, it is unpredictable whether the instruction-fetching event is indicated. Similarly, when an access exception prohibits access to all or a portion of the target of EXECUTE, it is unpredictable whether the instruction-fetching events for EXECUTE and the target are indicated.

2. When the operation is completed or partially completed, the event is indicated, regardless of whether any program exception, space-switch event, or monitor event is also recognized.

3. Successful branching, storage alteration, general-register alteration, and store using real address are not indicated for an operation or, in case the instruction is interruptible, for a unit of operation that is suppressed or nullified.

4. When the execution of the instruction is terminated, general-register or storage alteration is indicated whenever the event has occurred, and a model may indicate the event if the event would have occurred had the execution of the instruction been completed, even if altering the contents of the result field is contingent on operand values. For purposes of this definition, the occurrence of those exceptions which permit termination (addressing, protection, and data) is considered to cause termination, even if no result area is changed.

5. When LOAD PSW, PROGRAM RETURN, SET SYSTEM MASK, STORE THEN OR SYSTEM MASK, or SUPERVISOR CALL causes a PER condition and at the same time introduces a new PSW with the type of PSW-format error that is recognized immediately after the PSW becomes active, the interruption code identifies both the PER condition and the specification exception. When LOAD PSW, PROGRAM RETURN, or SUPERVISOR CALL introduces a PSW-format error of the type that is recognized as part of the execution of the following instruction, the PSW is stored as the old PSW without the specification exception being recognized.

    _____________________________ ______ ____________________________________ 
   |                             |      |             PER Event              |
   |                             | Type |______ ______ _______ _______ ______|
   |                             |  of  |      |Instr |Storage|  GR   |      |
   |  Concurrent Condition       |Ending|Branch|Fetch |Alter. |Alter.¹|STURA |
   |_____________________________|______|______|______|_______|_______|______|
   |Specification                |      |      |      |       |       |      |
   |   Odd instruction address   |  S   |  No  |  No  |  No   |  No   |  No  |
   |     in the PSW              |      |      |      |       |       |      |
   |Instruction access           |N or S|  No  |  U   |  No   |  No   |  No  |
   |Specification                |      |      |      |       |       |      |
   |   EXECUTE target address odd|  S   |  No  |  U   |  No   |  No   |  -   |
   |EXECUTE target access        |N or S|  No  |  U   |  No   |  No   |  -   |
   |Other nullifying             |  N   |  No  |  Yes |  No²  |  No²  |  -   |
   |Other suppressing            |  S   |  No  |  Yes |  No²  |  No²  |  No  |
   |All terminating              |  T   |  No  |  Yes |  Yes³ |  Yes³ |  -   |
   |All completing               |  C   |  Yes |  Yes |  Yes  |  Yes  |  -   |
   |_____________________________|______|______|______|_______|_______|______|
   |Explanation:                                                             |
   |                                                                         |
   |   -    The condition does not apply.                                    |
   |                                                                         |
   |   ¹    With PER 2, PER general-register-alteration events do not occur  |
   |        and are not indicated.                                           |
   |                                                                         |
   |   ²    Although PER events of this type are not indicated for the cur-  |
   |        rent unit of operation of an interruptible instruction, PER      |
   |        events of this type that were recognized on completed units of   |
   |        operation of the interruptible instruction are indicated.        |
   |                                                                         |
   |   ³    This event may be indicated, depending on the model, if the      |
   |        event has not occurred but would have been indicated if execu-   |
   |        tion had been completed.                                         |
   |                                                                         |
   |   C    The operation or, in the case of the interruptible instructions, |
   |        the unit of operation is completed.                              |
   |                                                                         |
   |   N    The operation or, in the case of the interruptible instructions, |
   |        the unit of operation is nullified.                              |
   |                                                                         |
   |   S    The operation or, in the case of the interruptible instructions, |
   |        the unit of operation is suppressed.                             |
   |                                                                         |
   |   T    The execution of the instruction is terminated.                  |
   |                                                                         |
   |   Yes  The PER event is indicated with the other program-interruption   |
   |        condition if the event has occurred; that is, the contents of    |
   |        the designated storage location or general register were al-     |
   |        tered, or an attempt was made to execute an instruction whose    |
   |        first byte is located in the designated storage area.            |
   |                                                                         |
   |   No   The PER event is not indicated.                                  |
   |                                                                         |
   |   U    It is unpredictable whether the PER event is indicated.          |
   |_________________________________________________________________________|

   Figure  4-5. Indication of PER Events with Other Concurrent Conditions

   Programming Notes:

1. The instruction-fetching event is indicated whenever the instruction is fetched for execution, regardless of whether it is the initial execution or a resumption, except that the event may be discarded (not indicated) if it is the only PER event to be indicated, the interruption is due to an asynchronous interruption condition or the performance of the stop function, and a unit of operation of the instruction remains to be executed.

2. The general-register-alteration event is indicated on the initial execution and on each resumption and does not depend on whether or not the register actually is changed.

3. The storage-alteration event is indicated only when data has been stored in the designated storage area by the portion of the operation starting with the last initiation and ending with the last byte transferred before the interruption. No special indication is provided on premature interruptions as to whether the event will occur again upon the resumption of the operation. When the designated storage area is a single byte location, a storage-alteration event can be recognized only once in the execution of MOVE LONG.

1. Check to see if the PER address is equal to the instruction address in the old PSW and if the last instruction executed was interruptible.

2. If both conditions are met, delete instruction-fetching and register-alteration events.

3. If both conditions are met and the event is storage alteration, delete the event if some part of the remaining destination operand is within the designated storage area.

   The  timing  facilities  include three facilities for measuring time:  the
   TOD clock, the clock comparator, and the CPU timer.

Subtopics:

• 4.6.1 Time-of-Day Clock
• 4.6.2 TOD-Clock Synchronization
• 4.6.3 Clock Comparator
• 4.6.4 CPU Timer

   The  time-of-day  (TOD)  clock  provides a high-resolution measure of real
   time suitable for the indication of date and time of day.   The  cycle  of
   the clock is approximately 143 years.

Subtopics:

• 4.6.1.1 Format
• 4.6.1.2 States
• 4.6.1.3 Changes in Clock State
• 4.6.1.4 Setting and Inspecting the Clock

   The  TOD  clock is a binary counter with the format shown in the following
   illustration.   The bit positions of the  clock  are  numbered  0  to  63,
   corresponding to the bit positions of a 64-bit unsigned binary integer.

                  1 microsecond___ 
                                  
    _____________________________ _ ______ 
   |                             | |      |
   |_____________________________|_|______|
   0                             51      63

   In  the  basic  form,  the TOD clock is incremented by adding a one in bit
   position 51 every microsecond.    In  models  having  a  higher  or  lower
   resolution,  a  different  bit position is incremented at such a frequency
   that the rate of advancing the clock is the same as if a one were added in
   bit position 51 every microsecond.   The resolution of the  TOD  clock  is
   such that the incrementing rate is comparable to the instruction-execution
   rate of the model.

   The  following  states are distinguished for the TOD clock:  set, not set,
   stopped, error, and not operational.  The state determines  the  condition
   code  set  by  execution of STORE CLOCK.  The clock is incremented, and is
   said to be running, when it is in either the  set  state  or  the  not-set
   state.

   When  the  TOD  clock  accessed  by  a  CPU  changes  value because of the
   execution of SET CLOCK or changes state, interruption  conditions  pending
   for  the  clock comparator, CPU timer, and TOD-clock-sync check may or may
   not be recognized for up to 1.048576 seconds (2²0 microseconds) after  the
   change.

   The  clock can be set to a specific value by execution of SET CLOCK if the
   manual TOD-clock control of  any  CPU  in  the  configuration  is  in  the
   enable-set  position.    Setting  the clock replaces the values in all bit
   positions from bit position 0  through  the  rightmost  position  that  is
   incremented  when  the  clock  is  running.   However, on some models, the
   rightmost bits starting at or to the right of  bit  52  of  the  specified
   value  are ignored, and zeros are placed in the corresponding positions of
   the clock.  The TOD clock can be inspected by executing STORE CLOCK, which
   causes a 64-bit value to be  stored.    Two  executions  of  STORE  CLOCK,
   possibly  on  different  CPUs  in  the  same  configuration,  always store
   different values if the clock  is  running  or,  if  separate  clocks  are
   accessed, both clocks are running and are synchronized.

   Programming Notes:

        ______ __________________________ 
       | TOD- |    Stepping Interval     |
       |Clock |____ _____ ____ __________|
       | Bit  |Days|Hours|Min.| Seconds  |
       |______|____|_____|____|__________|
       |  51  |                 0.000 001|
       |  47  |                 0.000 016|
       |  43  |                 0.000 256|
       |      |                          |
       |  39  |                 0.004 096|
       |  35  |                 0.065 536|
       |  31  |                 1.048 576|
       |      |                          |
       |  27  |                16.777 216|
       |  23  |             4  28.435 456|
       |  19  |       1    11  34.967 296|
       |      |                          |
       |  15  |      19     5  19.476 736|
       |  11  |  12  17    25  11.627 776|
       |   7  | 203  14    43   6.044 416|
       |   3  |3257  19    29  36.710 656|
       |______|__________________________|

        ______ ___ ___ ____ _____________________ 
       |      |   |   |Leap|                     |
       | Year |Mth|Day|Sec | Clock Setting (Hex) |
       |______|___|___|____|_____________________|
       | 1900 | 1 | 1 |    | 0000 0000 0000 0000 |
       | 1972 | 1 | 1 |    | 8126 D60E 4600 0000 |
       | 1972 | 7 | 1 |  1 | 820B A981 1E24 0000 |
       | 1973 | 1 | 1 |  2 | 82F3 00AE E248 0000 |
       | 1974 | 1 | 1 |  3 | 84BD E971 146C 0000 |
       | 1975 | 1 | 1 |  4 | 8688 D233 4690 0000 |
       | 1976 | 1 | 1 |  5 | 8853 BAF5 78B4 0000 |
       | 1977 | 1 | 1 |  6 | 8A1F E595 20D8 0000 |
       | 1978 | 1 | 1 |  7 | 8BEA CE57 52FC 0000 |
       | 1979 | 1 | 1 |  8 | 8DB5 B719 8520 0000 |
       | 1980 | 1 | 1 |  9 | 8F80 9FDB B744 0000 |
       | 1981 | 7 | 1 | 10 | 9230 5C0F CD68 0000 |
       | 1982 | 7 | 1 | 11 | 93FB 44D1 FF8C 0000 |
       | 1983 | 7 | 1 | 12 | 95C6 2D94 31B0 0000 |
       | 1985 | 7 | 1 | 13 | 995D 40F5 17D4 0000 |
       | 1988 | 1 | 1 | 14 | 9DDA 69A5 57F8 0000 |
       | 1990 | 1 | 1 | 15 | A171 7D06 3E1C 0000 |
       | 1991 | 1 | 1 | 16 | A33C 65C8 7040 0000 |
       | 1992 | 7 | 1 | 17 | A5EC 21FC 8664 0000 |
       | 1993 | 7 | 1 | 18 | A7B7 0ABE B888 0000 |
       | 1994 | 7 | 1 | 19 | A981 F380 EAAC 0000 |
       | 1996 | 1 | 1 | 20 | AC34 336F ECD0 0000 |
 |     | 1997 | 7 | 1 | 21 | AEE3 EFA4 02F4 0000 |
       |______|___|___|____|_____________________|

        _____________ __________________ 
       |  Interval   |Clock Units (Hex) |
       |_____________|__________________|
       |1 microsecond|              1000|
       |1 millisecond|           3E 8000|
       |1 second     |         F424 0000|
       |1 minute     |      39 3870 0000|
       |1 hour       |     D69 3A40 0000|
       |1 day        |  1 41DD 7600 0000|
       |365 days     |1CA E8C1 3E00 0000|
       |366 days     |1CC 2A9E B400 0000|
       |1,461 days*  |72C E4E2 6E00 0000|
       |_____________|__________________|
       |* Number of days in four years, |
       |  including a leap year.  Note  |
       |  that the year 1900 was not a  |
       |  leap year.  Thus, the four-   |
       |  year span starting in 1900    |
       |  has only 1,460 days.          |
       |________________________________|

   In  an  installation  with more than one CPU, each CPU may have a separate
   TOD clock, or more than one CPU may share a TOD clock,  depending  on  the
   model.  In all cases, each CPU has access to a single clock.

• Synchronizing the stepping rates for all TOD clocks in the configuration. Thus, if all clocks are set to the same value, they stay in synchronism.

• Comparing the rightmost 32 bits of each clock in the configuration. An unequal condition is signaled by an external interruption with the interruption code 1003 hex, indicating the TOD-clock-sync-check condition.

• Setting a TOD clock to the stopped state.

• Causing a stopped clock, with the TOD-clock-sync-control bit set to one, to start incrementing when bits 32-63 of any running clock in the configuration are incremented to zero. This permits the program to synchronize all clocks to any particular clock without requiring special operator action to select a "master clock" as the source of the clock-synchronization pulses.

   The  clock comparator provides a means of causing an interruption when the
   TOD-clock value exceeds a value specified by the program.

1. The TOD clock is running and the value of the clock comparator is less than the value in the compared portion of the clock, both values being considered unsigned binary integers. Comparison follows the rules of unsigned binary arithmetic.

2. The TOD clock is in the error state or the not-operational state.

The clock comparator can be inspected by executing the instruction STORE CLOCK COMPARATOR and can be set to a specific value by executing the SET CLOCK COMPARATOR instruction.

   Programming Notes:

   The  CPU  timer  provides  a  means for measuring elapsed CPU time and for
   causing an interruption when a specified amount of time has elapsed.

   Programming Notes:

Subtopics:

• 4.7.1 Resets
• 4.7.2 Initial Program Loading
• 4.7.3 Store Status
  

   Five reset functions are provided:

• CPU reset
• Initial CPU reset
• Subsystem reset
• Clear reset
• Power-on reset

Initial CPU reset provides the functions of CPU reset together with initialization of the current PSW, CPU timer, clock comparator, prefix, and control registers.

    ___________________ _______________________________________________ 
   |                   |            Function Performed on¹             |
   |                   |__________________ ____________ _______________|
   |                   | CPU on Which Key | Other CPUs | Remainder of  |
   |   Key Activated   |  Was Activated   | in Config  | Configuration |
   |___________________|__________________|____________|_______________|
   |System-reset-normal|CPU reset         |CPU reset   |Subsystem reset|
   |key                |                  |            |               |
   |                   |                  |            |               |
   |System-reset-clear |Clear reset²      |Clear reset²|Clear reset³   |
   |key                |                  |            |               |
   |                   |                  |            |               |
   |Load-normal key    |Initial CPU reset,|CPU reset   |Subsystem reset|
   |                   |followed by IPL   |            |               |
   |                   |                  |            |               |
   |Load-clear key     |Clear reset²,     |Clear reset²|Clear reset³   |
   |                   |followed by IPL   |            |               |
   |___________________|__________________|____________|_______________|
   |Explanation:                                                       |
   |                                                                   |
   | ¹ Activation of a system-reset or load key may change the config- |
   |   uration, including the connection with I/O, storage units, and  |
   |   other CPUs.                                                     |
   |                                                                   |
   | ² Only the CPU elements of this reset apply.                      |
   |                                                                   |
   | ³ Only the non-CPU elements of this reset apply.                  |
   |___________________________________________________________________|

   Figure  4-6. Manual Initiation of Resets

    _____________________________ _________________________________ 
   |                             |          Reset Function         |
   |                             |______ _____ _______ ______ _____|
   |                             | Sub- |     |Initial|      |Power|
   |                             |system| CPU |  CPU  |Clear | -On |
   |      Area Affected          |Reset |Reset| Reset |Reset |Reset|
   |_____________________________|______|_____|_______|______|_____|
   |CPU                          |  U   |  S  |   S¹  |  S¹  |  S  |
   |PSW                          |  U   | U/V |   C*¹ |  C*¹ |  C* |
   |Prefix                       |  U   | U/V |   C   |  C   |  C  |
   |CPU timer                    |  U   | U/V |   C   |  C   |  C  |
   |Clock comparator             |  U   | U/V |   C   |  C   |  C  |
   |Control registers            |  U   | U/V |   I   |  I   |  I  |
   |Access registers             |  U   | U/V |  U/V  |  C   |  C  |
   |General registers            |  U   | U/V |  U/V  |  C   |  C  |
   |Floating-point registers     |  U   | U/V |  U/V  |  C   |  C  |
   |Vector-facility registers    |  U   | U/V |  U/V  |  C   |  C  |
   |Storage keys                 |  U   |  U  |   U   |  C   |  C² |
   |Volatile main storage        |  U   |  U  |   U   |  C   |  C² |
   |Nonvolatile main storage     |  U   |  U  |   U   |  C   |  U  |
   |Expanded storage             |  U³  |  U³ |   U³  |  U³  |  C² |
   |TOD clock                    |  U4  |  U4 |   U4  |  U4  |  T² |
   |Floating interruption        |  C   |  U  |   U   |  C   |  C² |
   |  conditions                 |      |     |       |      |     |
   |I/O system                   |  R   |  U  |   U   |  R   |  R5 |
 | |PERFORM LOCKED OPERATION     |  U   |  U  |   U   |  RC  |  RP |
 | |  locks                      |      |     |       |      |     |
   |_____________________________|______|_____|_______|______|_____|
   |Explanation:                                                   |
   |                                                               |
   | *    Clearing the contents of the PSW to zero causes the PSW  |
   |      to be invalid.                                           |
   |                                                               |
   | ¹    When the IPL sequence follows the reset function on that |
   |      CPU, the CPU does not necessarily enter the stopped      |
   |      state, and the PSW is not necessarily cleared to zeros.  |
   |                                                               |
   | ²    When these units are separately powered, the  action is  |
   |      performed only when the power for the unit is turned on. |
   |                                                               |
   | ³    Access to change expanded storage at the time a reset    |
   |      function is performed may cause the contents of the 4K-  |
   |      byte block in expanded storage to be unpredictable.      |
   |      Access to examine expanded storage does not affect the   |
   |      contents of the expanded storage.                        |
   |                                                               |
   | 4    Access to the TOD clock by means of STORE CLOCK at the   |
   |      time a reset function is performed does not cause the    |
   |      value of the TOD clock to be affected.                   |
   |                                                               |
   | 5    When the channel subsystem is separately powered or con- |
   |      sists of multiple elements which are separately powered, |
   |      the reset action is applied only to those subchannels,   |
   |      channel paths, and I/O control units and devices on those|
   |      paths associated with the element which is being powered |
   |      on.                                                      |
   |_______________________________________________________________|
    _______________________________________________________________ 
   |Explanation (Continued):                                       |
   |                                                               |
   | C    The condition or contents are cleared.  If the area      |
   |      affected is a field, the contents are set to zero with   |
   |      valid checking-block code.                               |
   |                                                               |
   | I    The state or contents are initialized.  If the area af-  |
   |      fected is a field, the contents are set to the initial   |
   |      value with valid checking-block code.                    |
   |                                                               |
   | R    I/O-system reset is  performed in the channel subsystem. |
   |      As part of this reset, system reset is signaled to all   |
   |      I/O control units and devices attached to the channel    |
   |      subsystem.                                               |
   |                                                               |
 | | RC   All locks in the configuration are released.             |
 | |                                                               |
 | | RP   All locks in the configuration are released except for   |
 | |      ones held by CPUs already powered on.                    |
   |                                                               |
   | S    The CPU is reset; current operations, if any, are term-  |
   |      inated; the ALB and TLB are cleared of entries; inter-   |
   |      ruption conditions in the CPU are cleared; and the CPU   |
   |      is placed in the stopped state.  The effect of perform-  |
   |      ing the start function is unpredictable when the stopped |
   |      state has been entered by means of a reset.              |
   |                                                               |
   | T    The TOD clock is initialized to zero and validated; it   |
   |      enters the not-set state.                                |
   |                                                               |
   | U    The state, condition, or contents of the field remain    |
   |      unchanged.  However, the result is unpredictable if an   |
   |      operation is in progress that changes the state, con-    |
   |      dition, or contents of the field at the time of reset.   |
   |                                                               |
   | U/V  The contents remain unchanged, provided the field is not |
   |      being changed at the time the reset function is per-     |
   |      formed.  However, on some models the checking-block code |
   |      of the contents may be made valid.  The result is un-    |
   |      predictable if an operation is in progress that changes  |
   |      the contents of the field at the time of reset.          |
   |_______________________________________________________________|

   Figure  4-7. Summary of Reset Actions

Subtopics:

• 4.7.1.1 CPU Reset
• 4.7.1.2 Initial CPU Reset
• 4.7.1.3 Subsystem Reset
• 4.7.1.4 Clear Reset
• 4.7.1.5 Power-On Reset

   CPU reset causes the following actions:

1. The execution of the current instruction or other processing sequence, such as an interruption, is terminated, and all program-interruption and supervisor-call-interruption conditions are cleared.

2. Any pending external-interruption conditions which are local to the CPU are cleared. Floating external-interruption conditions are not cleared.

3. Any pending machine-check-interruption conditions and error indications which are local to the CPU and any check-stop states are cleared. Floating machine-check-interruption conditions are not cleared. Any machine-check condition which is reported to all CPUs in the configuration and which has been made pending to a CPU is said to be local to the CPU.

4. All copies of prefetched instructions or operands are cleared. Additionally, any results to be stored because of the execution of instructions in the current checkpoint interval are cleared.

5. The ART-lookaside buffer and translation-lookaside buffer are cleared of entries.

6. The CPU is placed in the stopped state after actions 1-5 have been completed. When the IPL sequence follows the reset function on that CPU, the CPU enters the load state at the completion of the reset function and does not necessarily enter the stopped state during the execution of the reset operation.

When the reset function in the CPU is initiated at the time the CPU is executing an I/O instruction or is performing an I/O interruption, the current operation between the CPU and the channel subsystem may or may not be completed, and the resultant state of the associated channel-subsystem facility may be unpredictable.

   Initial  CPU  reset  combines  the  CPU reset functions with the following
   clearing and initializing functions:

1. The contents of the current PSW, prefix, CPU timer, and clock comparator are set to zero. When the IPL sequence follows the reset function on that CPU, the contents of the PSW are not necessarily set to zero.

2. The contents of control registers are set to their initial value.

Setting the current PSW to zero causes the PSW to be invalid, since PSW bit 12 must be one. Thus, if the CPU is placed in the operating state after a reset without first introducing a new PSW, a specification exception is recognized.

   Subsystem reset operates only on those elements in the configuration which
   are not CPUs. It performs the following actions:

1. I/O-system reset is performed by the channel subsystem (see "I/O-System Reset" in topic 17.2.2.2).

2. All floating interruption conditions in the configuration are cleared.

   Clear  reset  combines the initial-CPU-reset function with an initializing
   function which causes the following actions:

1. The access, general, and floating-point registers of those CPUs which are in the configuration are set to zero.

2. The registers (vector-status register, vector-mask register, vector-activity count, and all vector registers) of those vector facilities, if any, which are in the configuration are cleared to zero with valid checking-block code.

3. The contents of the main storage in the configuration and the associated storage keys are set to zero with valid checking-block code.

4. | The locks used by all CPUs in the configuration when executing the
   | PERFORM LOCKED OPERATION instruction are released.

5. A subsystem reset is performed.

Programming Notes:

   The power-on-reset function for a component of the machine is performed as
   part of the power-on sequence for that component.

   Initial  program  loading  (IPL)  provides  a  manual  means for causing a
   program to be read from a designated device and for  initiating  execution
   of that program.

   The  store-status  operation  places  the  contents  of the CPU registers,
   except for the TOD clock, in assigned storage locations.

    __________________________ ________ __________ 
   |                          | Length | Absolute |
   |         Field            |in Bytes| Address  |
   |__________________________|________|__________|
   | CPU timer                |    8   |    216   |
   | Clock comparator         |    8   |    224   |
   | Current PSW              |    8   |    256   |
   | Prefix                   |    4   |    264   |
   | Access registers 0-15    |   64   |    288   |
   | Fl-pt registers 0-6      |   32   |    352   |
   | General registers 0-15   |   64   |    384   |
   | Control registers 0-15   |   64   |    448   |
   |__________________________|________|__________|

   Figure  4-8. Assigned Storage Locations for Store Status

   The multiprocessing facility provides for the interconnection of CPUs, via
   a  common  main  storage,  in  order to enhance system availability and to
   share data and resources.    The  multiprocessing  facility  includes  the
   following facilities:

• Shared main storage
• CPU-to-CPU interconnection
• TOD-clock synchronization

Subtopics:

• 4.8.1 Shared Main Storage
• 4.8.2 CPU-Address Identification

   The  shared-main-storage facility permits more than one CPU to have access
   to common main-storage locations.   All CPUs having  access  to  a  common
   main-storage  location  have access to the entire 4K-byte block containing
   that location and to the associated storage key.   The  channel  subsystem
   and  all CPUs in the configuration refer to a shared main-storage location
   using the same absolute address.

   Each  CPU  has  a  number assigned, called its CPU address.  A CPU address
   uniquely identifies one CPU within a configuration.  The CPU is designated
   by specifying this address in the CPU-address field of  SIGNAL  PROCESSOR.
   The  CPU signaling a malfunction alert, emergency signal, or external call
   is identified by storing this address in the CPU-address  field  with  the
   interruption.   The CPU address is assigned during system installation and
   is not changed as a result of reconfiguration changes.   The  program  can
   determine the address of the CPU by using STORE CPU ADDRESS.

   The CPU-signaling-and-response facility consists of SIGNAL PROCESSOR and a
   mechanism  to  interpret  and  act  on several order codes.   The facility
   provides for communications among CPUs, including transmitting, receiving,
   and decoding a set of  assigned  order  codes;  initiating  the  specified
   operation;  and responding to the signaling CPU.  A CPU can address SIGNAL
   PROCESSOR to  itself.    SIGNAL  PROCESSOR  is  described  in  Chapter 10,
   "Control Instructions."

Subtopics:

• 4.9.1 Signal-Processor Orders
• 4.9.2 Conditions Determining Response

   The  signal-processor  orders  are specified in bit positions 24-31 of the
   second-operand address of SIGNAL PROCESSOR and are  encoded  as  shown  in
   Figure 4-9.

    _______ __________________________ 
   | Code  |         Order            |
   |_______|__________________________|
   |  00   | Unassigned               |
   |  01   | Sense                    |
   |  02   | External call            |
   |  03   | Emergency signal         |
   |  04   | Start                    |
   |  05   | Stop                     |
   |  06   | Restart                  |
   |  07   | Unassigned               |
   |  08   | Unassigned               |
   |  09   | Stop and store status    |
   |  0A   | Unassigned               |
   |  0B   | Initial CPU reset        |
   |  0C   | CPU reset                |
   |  0D   | Set prefix               |
   |  0E   | Store status at address  |
   | 0F-FF | Unassigned               |
   |_______|__________________________|

   Figure  4-9. Encoding of Orders

   The orders are defined as follows:

   The parameter register has the following format:
    _ __________________ _____________ 
   |/|   Prefix Value   |/////////////|
   |_|__________________|_____________|
   0  1                 20           31

   The set-prefix order is completed as follows:

• If the addressed CPU is not in the stopped state, the order is not accepted. Instead, bit 22 (incorrect state) of the general register designated by the R1 field of the SIGNAL PROCESSOR instruction is set to one, and condition code 1 is set.

• The value to be placed in the prefix register of the addressed CPU is tested for availability. The absolute address of a 4K-byte area of storage is formed by appending 12 zeros to the right of bits 1-19 of the parameter value. This address is treated as a 31-bit absolute address regardless of whether the sending and receiving CPUs are in the 24-bit or 31-bit addressing mode. The 4K-byte block of storage at this address is accessed. The access is not subject to protection, and the associated reference bit may or may not be set to one. If the block is not available in the configuration, the order is not accepted by the addressed CPU, bit 23 (invalid parameter) of the general register designated by the R1 field of the SIGNAL PROCESSOR instruction is set to one, and condition code 1 is set.

• The value is placed in the prefix register of the addressed CPU.

• The ALB and TLB of the addressed CPU are cleared of their contents.

• A serializing and checkpoint-synchronizing function is performed on the addressed CPU following insertion of the new prefix value.

   The parameter register has the following format:
    _ ______________________ _________ 
   |/|  Status-Area Origin  |/////////|
   |_|______________________|_________|
   0  1                     23       31

   The store-status-at-address order is completed as follows:

• If the addressed CPU is not in the stopped state, the order is not accepted. Instead, bit 22 (incorrect state) of the general register designated by the R1 field of the SIGNAL PROCESSOR instruction is set to one, and condition code 1 is set.

• The address of the area into which status is to be stored is tested for availability. The absolute address of a 512-byte area of storage is formed by appending nine zeros to the right of bits 1-22 of the parameter value. This address is treated as a 31-bit absolute address regardless of whether the sending and receiving CPUs are in the 24-bit or 31-bit addressing mode. The 512-byte block of storage at this address is accessed. The access is not subject to protection, and the associated reference bit may or may not be set to one. If the block is not available in the configuration, the order is not accepted by the addressed CPU, bit 23 (invalid parameter) of the general register designated by the R1 field of the SIGNAL PROCESSOR instruction is set to one, and condition code 1 is set.

• The status of the addressed CPU is placed in the designated area. The information stored, and the format of the area receiving the information, are the same as for the stop-and-store-status order, except that each field, rather than being stored at an offset from the beginning of absolute storage, is stored in the designated area at an offset that is the same as that for the absolute area. Bytes 0-215, 232-255, and 268-287 of the designated area remain unchanged. (See "Store Status" in topic 4.7.3).

• A serialization and checkpoint-synchronization function is performed on the addressed CPU following storing of the status.

Subtopics:

• 4.9.2.1 Conditions Precluding Interpretation of the Order Code
• 4.9.2.2 Status Bits
  

   The  following  situations  preclude  the  initiation  of the order.   The
   sequence in which the situations are listed is the order of  priority  for
   indicating concurrently existing situations:

1. The access path to the addressed CPU is busy because a concurrently executed SIGNAL PROCESSOR is using the CPU-signaling-and-response facility. The CPU which is concurrently executing the instruction can be any CPU in the configuration other than this CPU, and the CPU address can be any address, including that of this CPU or an invalid address. The order is rejected. Condition code 2 is set.

2. The addressed CPU is not operational; that is, it is not provided in the installation, it is not in the configuration, it is in any of certain customer-engineer test modes, or its power is off. The order is rejected. Condition code 3 is set. This condition cannot arise as a result of a SIGNAL PROCESSOR by a CPU addressing itself.

3. One of the following conditions exists at the addressed CPU:
   1. A previously issued start, stop, restart, stop-and-store-status, set-prefix, or store-status-at-address order has been accepted by the addressed CPU, and execution of the function requested by the order has not yet been completed.

   2. A manual start, stop, restart, or store-status function has been initiated at the addressed CPU, and the function has not yet been completed. This condition cannot arise as a result of a SIGNAL PROCESSOR by a CPU addressing itself.

   If the currently specified order is sense, external call, emergency signal, start, stop, restart, stop and store status, set prefix, or store status at address, then the order is rejected, and condition code 2 is set. If the currently specified order is one of the reset orders, or an unassigned or not-implemented order, the order code is interpreted as described in "Status Bits" in topic 4.9.2.2.

4. One of the following conditions exists at the addressed CPU:
   1. A previously issued initial-CPU-reset or CPU-reset order has been accepted by the addressed CPU, and execution of the function requested by the order has not yet been completed.

   2. A manual-reset function has been initiated at the addressed CPU, and the function has not yet been completed. This condition cannot arise as a result of a SIGNAL PROCESSOR by a CPU addressing itself.

   If the currently specified order is sense, external call, emergency signal, start, stop, restart, stop and store status, set prefix, or store status at address, then the order is rejected, and condition code 2 is set. If the currently specified order is one of the reset orders, or an unassigned or not-implemented order, either the order is rejected and condition code 2 is set or the order code is interpreted as described in "Status Bits" in topic 4.9.2.2.

When the conditions described in items 1 and 2 above do not apply and operator-intervening and receiver-check status conditions do not exist at the addressed CPU, reset orders may be accepted regardless of whether the addressed CPU has completed a previously accepted order. This may cause the previous order to be lost when it is only partially completed, making unpredictable whether the results defined for the lost order are obtained.

   Various  status  conditions  are defined whereby the issuing and addressed
   CPUs can indicate their responses to the  specified  order.    The  status
   conditions  and  their bit positions in the general register designated by
   the R1 field of the SIGNAL PROCESSOR instruction are shown in Figure 4-10.

    __________ __________________________ 
   |   Bit    |                          |
   | Position |     Status Condition     |
   |__________|__________________________|
   |    0     | Equipment check          |
   |    1-21  | Unassigned; zeros stored |
   |    22    | Incorrect state          |
   |    23    | Invalid parameter        |
   |    24    | External-call pending    |
   |    25    | Stopped                  |
   |    26    | Operator intervening     |
   |    27    | Check stop               |
   |    28    | Unassigned; zero stored  |
   |    29    | Inoperative              |
   |    30    | Invalid order            |
   |    31    | Receiver check           |
   |__________|__________________________|

   Figure  4-10. Status Conditions

   The status condition assigned to bit position 0 is generated  by  the  CPU
   executing SIGNAL PROCESSOR.  The remaining status conditions are generated
   by the addressed CPU.

1. Status bits 22-27 and 29 indicate the presence of the corresponding conditions in the addressed CPU at the time the order code is received. Except in response to the sense order, each condition is indicated only when the condition precludes the successful execution of the specified order, although invalid parameter is not necessarily indicated when any other precluding condition exists. In the case of sense, all existing status conditions are indicated; the operator-intervening condition is indicated if it precludes the execution of any installed order.

2. Status bits 30 and 31 indicate that the corresponding conditions were detected by the addressed CPU during reception of the order.

The status conditions are defined as follows:

   Status Condition

   31 Receiver check&ne. ____________________ 
   30 Invalid order ____________________  |
   29 Inoperative ____________________  | |
   27 Check stop ___________________  | | |
   26 Operator intervening# ______  | | | |
   25 Stopped __________________  | | | | |
   24 External call pending __  | | | | | |
   23 Invalid parameter ____  | | | | | | |
   22 Incorrect state ____  | | | | | | | |
                          | | | | | | | | |
                          | | | | | | | | |
   Order                  | | | | | | | | |
                                  
   Sense                  0 0 X X X X 0 0 X
   External call          0 0 X 0 X X 0 0 X
   Emergency signal       0 0 0 0 X X 0 0 X
   Start                  0 0 0 0 X X X 0 X
   Stop                   0 0 0 0 X X X 0 X
   Restart                0 0 0 0 X X X 0 X
   Stop and store status  0 0 0 0 X X X 0 X
   Initial CPU reset      0 0 0 0 X 0 X 0 X
   CPU reset              0 0 0 0 X 0 X 0 X
   Set prefix             X X 0 0 X X X 0 X
   Store status at addr.  X X 0 0 X X X 0 X
   Unassigned order       0 0 0 0 X E X 1 X

   If the presented status bits are all zeros, the order has  been  accepted,
   and  the  issuing  CPU  sets  condition  code 0.   If one or more ones are
   presented, the order has been rejected, and the  issuing  CPU  stores  the
   status  in  the  general register designated by the R1 field of the SIGNAL
   PROCESSOR instruction and sets condition code 1.

   Programming Notes:

1. Sense indicates whether an external-call condition is pending.

2. External call and emergency signal cause the corresponding interruption conditions to be generated. External call can be rejected because of a previously generated external-call condition.

3. Start sets condition code 0 and has no other effect.

4. Stop causes the CPU to set condition code 0, take pending interruptions for which it is enabled, and enter the stopped state.

5. Restart provides a means to store the current PSW.

6. Stop and store status causes the machine to stop and store all current status.

   Normally,  operation  of  the CPU is controlled by instructions in storage
   that are executed sequentially, one  at  a  time,  left  to  right  in  an
   ascending  sequence  of  storage  addresses.    A change in the sequential
   operation may be caused by  branching,  LOAD  PSW,  interruptions,  SIGNAL
   PROCESSOR orders, or manual intervention.

Subtopics:

• 5.1 Instructions
• 5.2 Address Generation
• 5.3 Instruction Execution and Sequencing
• 5.4 Authorization Mechanisms
• 5.5 PC-Number Translation
• 5.6 Home Address Space
• 5.7 Access-Register Introduction
• 5.8 Access-Register Translation
• 5.9 Subspace Groups
• 5.10 Linkage-Stack Introduction
• 5.11 Extended Entry-Table Entries
• 5.12 Linkage-Stack Operations
• 5.13 Sequence of Storage References
• 5.14 Serialization

   Each instruction consists of two major parts:

• An operation code (op code), which specifies the operation to be performed

• The designation of the operands that participate

Subtopics:

• 5.1.1 Operands
• 5.1.2 Instruction Formats

   Operands  can be grouped in three classes:  operands located in registers,
   immediate operands, and operands in  storage.    Operands  may  be  either
   explicitly or implicitly designated.

1. Specify a complete address by using an abbreviated notation

2. Perform address manipulation using instructions which employ general registers for operands

3. Modify addresses by program means without alteration of the instruction stream

4. Operate independent of the location of data areas by directly using addresses received from other programs

When the CPU is in the access-register mode, a B or R field may designate an access register in addition to being used to specify an address.

   An  instruction  is  one,  two,  or  three halfwords in length and must be
   located in storage on a halfword boundary.  Each instruction is in one  of
   eleven  basic  formats:   E, RR, RRE, RX, RS, RSI, RI, SI, S, SSE, and SS,
   with three variations of SS.  (See Figure 5-1.)

   E Format

    __________________ 
   |      Op Code     |
   |__________________|
   0                 15
   RR Format

    ________ ____ ____ 
   | Op Code| R1 | R2 |
   |________|____|____|
   0         8   12  15
   RRE Format

    _________________ ________ ____ ____ 
   |     Op Code     |////////| R1 | R2 |
   |_________________|________|____|____|
   0                 16       24   28  31
   RX Format

    ________ ____ ____ ____ ____________ 
   | Op Code| R1 | X2 | B2 |     D2     |
   |________|____|____|____|____________|
   0         8   12   16   20          31
   RS Format

    ________ ____ ____ ____ ____________ 
   | Op Code| R1 | R3 | B2 |     D2     |
   |________|____|____|____|____________|
   0         8   12   16   20          31
   RSI Format

    ________ ____ ____ _________________ 
   | Op Code| R1 | R3 |       I2        |
   |________|____|____|_________________|
   0         8   12   16               31
   RI Format

    ________ ____ ____ _________________ 
   | Op Code| R1 |OpCd|       I2        |
   |________|____|____|_________________|
   0         8   12   16               31
   SI Format

    ________ _________ ____ ____________ 
   | Op Code|    I2   | B1 |     D1     |
   |________|_________|____|____________|
   0         8        16   20          31
   S Format

    __________________ ____ ____________ 
   |    Op Code       | B2 |     D2     |
   |__________________|____|____________|
   0                  16   20          31
   SS Format

    ________ _________ ____ _/__ ____ _/__ 
   | Op Code|    L    | B1 | D1 | B2 | D2 |
   |________|_________|____|_/__|____|_/__|
   0         8        16   20   32   36  47

    ________ ____ ____ ____ _/__ ____ _/__ 
   | Op Code| L1 | L2 | B1 | D1 | B2 | D2 |
   |________|____|____|____|_/__|____|_/__|
   0         8   12   16   20   32   36  47

    ________ ____ ____ ____ _/__ ____ _/__ 
   | Op Code| R1 | R3 | B1 | D1 | B2 | D2 |
   |________|____|____|____|_/__|____|_/__|
   0         8   12   16   20   32   36  47
   SSE Format

    __________________ ____ _/__ ____ _/__ 
   |      Op Code     | B1 | D1 | B2 | D2 |
   |__________________|____|_/__|____|_/__|
   0                  16   20   32   36  47

   Figure  5-1. Basic Instruction Formats

   Some instructions contain fields that vary slightly from the basic format,
   and in some instructions the  operation  performed  does  not  follow  the
   general  rules  stated  in  this  section.    All  of these exceptions are
   explicitly identified in the individual instruction descriptions.

• E denotes an operation using implied operands and having an extended op-code field.
• RR denotes a register-and-register operation.
• RRE denotes a register-and-register operation having an extended op-code field.
• RX denotes a register-and-indexed-storage operation.
• RS denotes a register-and-storage operation.
• RSI denotes a register-and-immediate operation.
• RI denotes a register-and-immediate operation having an extended op-code.
• SI denotes a storage-and-immediate operation.
• S denotes an operation using an implied operand and storage.
• SS denotes a storage-and-storage operation.
• SSE denotes a storage-and-storage operation having an extended op-code field.

The first two bits of the first or only byte of the op code specify the length and format of the instruction, as follows:

    _________ _____________ _____________________ 
   |   Bit   | Instruction |                     |
   |Positions| Length (in  |     Instruction     |
   |   0-1   | Halfwords)  |       Format        |
   |_________|_____________|_____________________|
   |   00    |     One     |        E/RR         |
   |   01    |     Two     |         RX          |
   |   10    |     Two     |RI/RRE/RS/RSI/RX/S/SI|
   |   11    |    Three    |       SS/SSE        |
   |_________|_____________|_____________________|

   In  the  format  illustration for each individual instruction description,
   the op-code field or fields show the op code as hexadecimal digits  within
   single  quotes.    The  hexadecimal representation uses 0-9 for the binary
   codes 0000-1001 and A-F for the binary codes 1010-1111.

Subtopics:

• 5.1.2.1 Register Operands
• 5.1.2.2 Immediate Operands
• 5.1.2.3 Storage Operands

    In the RR, RRE, RX, RS, RSI, and RI formats, the contents of the register
   designated  by  the  R1  field are called the first operand.  The register
   containing  the  first  operand  is   sometimes   referred   to   as   the
   "first-operand  location,"  and  sometimes as "register R1." In the RR and
   RRE formats, the R2 field designates the register  containing  the  second
   operand,  and  the R2 field may designate the same register as R1.  In the
   RS and RSI formats, the use of the R3 field depends on the instruction.

   In  the SI format, the contents of the eight-bit immediate-data field, the
   I2 field of the instruction, are used directly as the second operand.  The
   B1 and D1 fields specify the first operand, which is one byte in length.

   The  use  of  B  and  R  fields  to designate access registers to refer to
   storage  operands  is  described  in  "Access-Register-Specified   Address
   Spaces" in topic 5.7.2.1.

Subtopics:

• 5.2.1 Bimodal Addressing
• 5.2.2 Sequential Instruction-Address Generation
• 5.2.3 Operand-Address Generation
• 5.2.4 Branch-Address Generation
  

   Bit  32  of the current PSW is the addressing-mode bit.  This bit controls
   the size of the effective address produced by address  generation.    When
   bit  32  of  the  current PSW is zero, the CPU is in the 24-bit addressing
   mode,  and  24-bit  instruction  and  operand  effective   addresses   are
   generated.    When  bit  32  of  the current PSW is one, the CPU is in the
   31-bit addressing mode,  and  31-bit  instruction  and  operand  effective
   addresses are generated.

   When an instruction is fetched from the location designated by the current
   PSW,  the  instruction  address is increased by the number of bytes in the
   instruction, and the instruction is executed.   The same  steps  are  then
   repeated  by  using  the new value of the instruction address to fetch the
   next instruction in the sequence.

Subtopics:

• 5.2.3.1 Formation of the Intermediate Value
• 5.2.3.2 Formation of the Operand Address
  

   An  operand address that refers to storage is derived from an intermediate
   value, which either is contained in a register designated by an R field in
   the instruction or is calculated from the sum  of  three  binary  numbers:
   base address, index, and displacement.

   The  generated  operand  address  is always 31 bits long, and the bits are
   numbered 1-31.  In some portions of this document, the  generated  address
   may  be  referred  to  as being 32 bits long, with the bits numbered 0-31.
   Bit 0 of the generated address is always forced to be zero.  The manner in
   which the generated  address  is  obtained  from  the  intermediate  value
   depends  on  the  current addressing mode.  In the 24-bit addressing mode,
   bits 0-7 of the intermediate value are ignored, bits 0-7 of the  generated
   address  are  forced  to be zeros, and bits 8-31 of the intermediate value
   become bits 8-31 of the generated address.  In the 31-bit addressing mode,
   bit 0 of the intermediate value is ignored, bit 0 of the generated address
   is forced to be zero, and bits 1-31 of the intermediate value become  bits
   1-31 of the generated address.

Subtopics:

• 5.2.4.1 Formation of the Intermediate Value
• 5.2.4.2 Formation of the Branch Address
  

5.2.4.1 Formation of the Intermediate Value

   For  branch  instructions,  the  address  of  the  next  instruction to be
   executed when the branch is taken is called the branch address.  Depending
   on the branch instruction, the instruction format may be RI, RR, RS,  RSI,
   or RX.

   The  branch  address  is always 31 bits long, with the bits numbered 1-31.
   The branch address replaces bits 33-63 of the current PSW.  The manner  in
   which  the  branch address is obtained from the intermediate value depends
   on the addressing mode.  For those branch instructions  which  change  the
   addressing  mode,  the  new  addressing  mode  is  used.    In  the 24-bit
   addressing mode, bits 0-7 of the intermediate value are ignored, bits  1-7
   of  the  branch  address are made zeros, and bits 8-31 of the intermediate
   value become bits 8-31 of the branch address.   In the  31-bit  addressing
   mode,  bit  0  of  the intermediate value is ignored, and bits 1-31 of the
   intermediate value become bits 1-31 of the branch address.

   The  program-status word (PSW), described in Chapter 4, "Control" contains
   information required for proper program execution.   The PSW  is  used  to
   control  instruction sequencing and to hold and indicate the status of the
   CPU in relation to the program currently being executed.   The  active  or
   controlling PSW is called the current PSW.

Subtopics:

• 5.3.1 Decision Making
• 5.3.2 Loop Control
• 5.3.3 Subroutine Linkage without the Linkage Stack
• 5.3.4 Interruptions
• 5.3.5 Types of Instruction Ending
• 5.3.6 Interruptible Instructions
• 5.3.7 Exceptions to Nullification and Suppression

   Facilities  for  decision  making  are provided by BRANCH ON CONDITION and
   BRANCH RELATIVE ON CONDITION.  This instruction inspects a condition  code
   that reflects the result of a majority of the arithmetic, logical, and I/O
   operations.   The condition code, which consists of two bits, provides for
   four possible condition-code settings:  0, 1, 2, and 3.

   Loop control can be performed by the use of BRANCH ON CONDITION and BRANCH
   RELATIVE  ON  CONDITION.    to  test the outcome of address arithmetic and
   counting operations.   For  some  particularly  frequent  combinations  of
   arithmetic and tests, BRANCH ON COUNT, BRANCH ON INDEX HIGH, and BRANCH ON
   INDEX  LOW OR EQUAL are provided, and relative-branch equivalents of these
   instructions are  also  provided.    These  branches,  being  specialized,
   provide increased performance for these tasks.

   This section describes only the methods for subroutine linkage that do not
   use the linkage stack.  For the linkage extensions provided by the linkage
   stack, see "Linkage-Stack Introduction" in topic 5.10.

    ___________ ______ _______________ _______________ _______________ _______________ _________ _______ 
   |           |      |  Instruction  |  Addressing   |    Problem    |     PASN      |         |       |
   |           |      |    Address    |     Mode      |     State     |      CR4      | PSW-Key |       |
   |           |      |PSW Bits 33-63 |  PSW Bit 32   |  PSW Bit 15   |  Bits 16-31   |  Mask   |       |
   |           |      |_______ _______|_______ _______|_______ _______|_______ _______| Changed |       |
   |Instruction|Format| Save  |  Set  | Save  |  Set  | Save  |  Set  | Save  |  Set  | in CR3  | Trace |
   |___________|______|_______|_______|_______|_______|_______|_______|_______|_______|_________|_______|
   |  BALR*    | RR   |  Yes  |  R2¹  |  AM   |   -   |   -   |   -   |   -   |   -   |    -    |  R2¹  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BAL*     | RX   |  Yes  |  Yes  |  AM   |   -   |   -   |   -   |   -   |   -   |    -    |   -   |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BASR     | RR   |  Yes  |  R2¹  |  Yes  |   -   |   -   |   -   |   -   |   -   |    -    |  R2¹  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BAS      | RX   |  Yes  |  Yes  |  Yes  |   -   |   -   |   -   |   -   |   -   |    -    |   -   |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BASSM    | RR   |  Yes  |  R2¹  |  Yes  |  R2¹  |   -   |   -   |   -   |   -   |    -    |  R2¹  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BRAS     | RI   |  Yes  |  Yes  |  Yes  |   -   |   -   |   -   |   -   |   -   |    -    |   -   |
   |           |      |       |       |       |       |       |       |       |       |         |       |
 | |  BSA-ba   | RRE  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes4 |   -   |   -   |"AND" R15|  Yes  |
 | |           |      |       |       |       |       |       |       |       |       |         |       |
 | |  BSA-ra   | RRE  |  R1¹  |  Yes  |  R1¹  |  Yes  |   -   |  Yes  |   -   |   -   |   Yes   |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BSG      | RRE  |  Yes  |  Yes  |  Yes  |  Yes  |   -   |   -   |   -   |   -³  |    -    |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  BSM      | RR   |   -   |  R2¹  |  R1¹  |  R2¹  |   -   |   -   |   -   |   -   |    -    |   -   |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  MC#²     | SI   |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |   -   |   -   |    -    |   -   |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  PC-cp    | S    |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |   -   |   -   |"OR" EKM |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  PC-ss    | S    |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |"OR" EKM |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  PT-cp    | RRE  |   -   |  R2   |   -   |  R2   |   -   |  R2** |   -   |   -   |"AND" R1 |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  PT-ss    | RRE  |   -   |  R2   |   -   |  R2   |   -   |  R2** |   -   |  Yes  |"AND" R1 |  Yes  |
   |           |      |       |       |       |       |       |       |       |       |         |       |
   |  SVC²     | RR   |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |  Yes  |   -   |   -   |    -    |   -   |
   |___________|______|_______|_______|_______|_______|_______|_______|_______|_______|_________|_______|
   |Explanation:                                                                                        |
   |                                                                                                    |
   |   -   No                                                                                           |
   |                                                                                                    |
   |   *   In the 24-bit addressing mode, the instruction-length code, condition code, program mask,    |
   |       and 24-bit instruction address are saved, and the 24-bit instruction address is set; in      |
   |       the 31-bit addressing mode, the addressing mode and the 31-bit instruction address are       |
   |       saved, and the 31-bit instruction address is set.                                            |
   |                                                                                                    |
   |   **  A change from the supervisor to the problem state is allowed; a privileged-operation excep-  |
   |       tion is recognized when a change from the problem to the supervisor state is specified.      |
   |                                                                                                    |
   |   #   Monitor-mask bits provide a means of disallowing linkage, or enabling linkage, for selected  |
   |       classes of events.                                                                           |
   |                                                                                                    |
   |   ¹   The action takes place only if the associated R field in the instruction is nonzero.         |
   |                                                                                                    |
   |   ²   MC and SVC, as part of the interruption, save the entire current PSW and load a new PSW.     |
   |                                                                                                    |
   |   ³   The primary segment-table designation is set even though the PASN is not set.                |
   |____________________________________________________________________________________________________|
    ____________________________________________________________________________________________________ 
   |Explanation (Continued):                                                                            |
 | |   4   The problem state is set.                                                                    |
 | |                                                                                                    |
 | |   5   The PSW key also is set from general register R1.                                            |
   |                                                                                                    |
   |   AM  Saved only if the 31-bit addressing mode is specified.                                       |
   |____________________________________________________________________________________________________|

   Figure  5-2. Summary of Linkage Instructions without the Linkage Stack

        L     15,VCONE
        BASSM 14,15

   The return from such a routine would normally be:

        BSM   0,14

   The BRANCH AND LINK (BAL, BALR)  instruction  is  provided  primarily  for
   compatibility  reasons.  It is defined to operate in the 31-bit addressing
   mode to increase the probability that an old, straightforward program  can
   be  modified  to  operate in the 31-bit addressing mode with minimal or no
   change.  It is recommended, however, that BRANCH AND SAVE (BAS  and  BASR)
   be  used  instead  and  that  BRANCH  AND  LINK be avoided since it places
   nonzero information in the left part of the general register in the 24-bit
   addressing mode, which may lead to problems.    Additionally,  BRANCH  AND
   LINK  is  likely to be slower than BRANCH AND SAVE because BRANCH AND SAVE
   always saves the right half of the PSW, whereas BRANCH AND LINK must  take
   additional  time to check the addressing mode, and then even more time, if
   in the 24-bit addressing mode, to construct the ILC, condition  code,  and
   program mask to be placed in the leftmost byte of the link register.

        BCR   15,14

   However, the standard "return instruction":

        BSM   0,14

   operates correctly for all cases except for a calling BAL executed in  the
   24-bit  addressing mode.  In the 24-bit addressing mode, BAL causes an ILC
   of 10 to be placed in the leftmost two bits of the link register.  Thus, a
   BSM would return in the 31-bit addressing mode.  Note that an  EXECUTE  of
   BALR in the 24-bit addressing mode also causes the same ILC effect.

        BCR   15,14

   or

        BSM   0,14

   In  some cases, it may be desirable to rewrite a program that is called by
   an old program which has not been rewritten.   In such  a  case,  the  old
   program,  which  operates in the 24-bit addressing mode, will be given the
   address of an intermediate program that will set up the correct entry  and
   return  modes  and  then  call  the rewritten program.   Such a program is
   sometimes referred to as a glue module.   The instruction BRANCH  AND  SET
   MODE  (BSM)  with  a  nonzero  R1 field provides the function necessary to
   perform this operation efficiently.  This is shown in Figure 5-3.

    ___________________________________________________________________ 
   |                                                                   |
   | Old Program              Glue Module               New Program    |
   |                                                                   |
   |         L    15,OLDVCON                                           |
   |         BALR 14,15                                                |
   |          °                                                        |
   |          °                                                        |
   |          °                                                        |
   | OLDVCON DC   V(GLUE)                                              |
   |                          GLUE    USING *,15                       |
   |                                  L     15,NEWVCON                 |
   |                                  BSM   14,15                      |
   |                          NEWVCON DC    V(NEW)                     |
   |                                                    NEW USING *,15 |
   |                                                         °         |
   |                                                         °         |
   |                                                         °         |
   |                                                        BSM   0,14 |
   |                                                                   |
   |___________________________________________________________________|

   Figure  5-3. Glue Module

   Interruptions  permit  the  CPU  to change state as a result of conditions
   external to the system, in subchannels or input/output (I/O)  devices,  in
   other  CPUs,  or in the CPU itself.  Details are to be found in Chapter 6,
   "Interruptions."

   Instruction   execution   ends   in   one  of  five  ways:     completion,
   nullification, suppression, termination, and partial completion.

Subtopics:

• 5.3.5.1 Completion
• 5.3.5.2 Suppression
• 5.3.5.3 Nullification
• 5.3.5.4 Termination

   Completion  of instruction execution provides results as called for in the
   definition of the instruction.   When an  interruption  occurs  after  the
   completion  of the execution of an instruction, the instruction address in
   the old PSW designates the next sequential instruction.

   Suppression of instruction execution causes the instruction to be executed
   as  if  it  specified  "no  operation." The contents of any result fields,
   including the condition code, are not changed.  The instruction address in
   the old PSW on an  interruption  after  suppression  designates  the  next
   sequential instruction.

   Nullification of instruction execution has the same effect as suppression,
   except  that  when  an  interruption  occurs  after  the  execution  of an
   instruction has been nullified, the instruction address  in  the  old  PSW
   designates  the  instruction  whose execution was nullified (or an EXECUTE
   instruction, as appropriate) instead of the next sequential instruction.

   Termination of instruction execution causes the contents of any fields due
   to  be  changed by the instruction to be unpredictable.  The operation may
   replace all, part, or none of the contents of the designated result fields
   and may change the condition code if such change  is  called  for  by  the
   instruction.    Unless  the  interruption  is  caused  by  a machine-check
   condition, the validity  of  the  instruction  address  in  the  PSW,  the
   interruption  code,  and  the  ILC  are not affected, and the state or the
   operation of  the  machine  is  not  affected  in  any  other  way.    The
   instruction  address  in  the old PSW on an interruption after termination
   designates the next sequential instruction.

Subtopics:

• 5.3.6.1 Point of Interruption
• 5.3.6.2 Unit of Operation
• 5.3.6.3 Execution of Interruptible Instructions
• 5.3.6.4 Condition-Code Alternative to Interruptibility
  

   For  most  instructions,  the  entire  execution  of an instruction is one
   operation.  An interruption is permitted between operations; that  is,  an
   interruption  can  occur after the performance of one operation and before
   the start of a subsequent operation.

• COMPARE AND FORM CODEWORD
• COMPARE LOGICAL LONG
• COMPARE UNTIL SUBSTRING EQUAL
• MOVE LONG
• TEST BLOCK
• UPDATE TREE
• Interruptible instructions of the vector facility (see the publication IBM Enterprise Systems Architecture/390 Vector Operations, SA22-7207)

   Whenever  points  of  interruption that include those occurring within the
   execution of an interruptible instruction are discussed, the term "unit of
   operation" is used.    For  a  noninterruptible  instruction,  the  entire
   execution consists, in effect, in the execution of one unit of operation.

   The  execution of an interruptible instruction is completed when all units
   of operation associated with that instruction  are  completed.    When  an
   interruption   occurs  after  completion,  inhibition,  nullification,  or
   suppression of a unit of operation, all preceding units of operation  have
   been  completed,  and  subsequent units of operation and instructions have
   not been started.  The main difference between these types  of  ending  is
   the  handling of the current unit of operation and whether the instruction
   address stored in the old PSW identifies the current  instruction  or  the
   next sequential instruction.

    ______________ _____________ _____________ ______________ 
   |    Unit of   | Instruction |   Operand   |Current Result|
   | Operation Is |   Address   |  Parameters |   Location   |
   |______________|_____________|_____________|______________|
   |Completed     |             |             |              |
   |  Last unit   |Next instruc-|Depends on   |Changed       |
   |   of oper-   | tion        | the instruc-|              |
   |   ation      |             | tion        |              |
   |  Any other   |Current in-  |Next unit of |Changed       |
   |   unit of    | struction   | operation   |              |
   |   operation  |             |             |              |
   |              |             |             |              |
   |Inhibited     |Current in-  |Next unit of |Unchanged     |
   |              | struction   | operation   |              |
   |              |             |             |              |
   |Nullified     |Current in-  |Current unit |Unchanged     |
   |              | struction   | of operation|              |
   |              |             |             |              |
   |Suppressed    |Next instruc-|Current unit |Unchanged     |
   |              | tion        | of operation|              |
   |              |             |             |              |
   |Terminated    |Next instruc-|Unpredictable|Unpredictable |
   |              | tion        |             |              |
   |______________|_____________|_____________|______________|

   Figure  5-4. Types of Ending for a Unit of Operation

5.3.6.4 Condition-Code Alternative to Interruptibility

   The  following instructions are not interruptible instructions but instead
   may be completed after  performing  a  CPU-determined  subportion  of  the
   processing specified by the parameters of the instructions:

• CHECKSUM
• COMPARE LOGICAL STRING
• COMPARE LOGICAL LONG EXTENDED
• MOVE LONG EXTENDED
• MOVE STRING
• SEARCH STRING

   In  certain unusual situations, the result fields of an instruction having
   a store-type operand  are  changed  in  spite  of  the  occurrence  of  an
   exception  which  would  normally  result in nullification or suppression.
   These situations are exceptions to the general rule that the operation  is
   treated  as  a  no-operation  when an exception requiring nullification or
   suppression is recognized.  Each of these situations  may  result  in  the
   turning  on of the change bit associated with the store-type operand, even
   though the final result in storage may appear unchanged.  Depending on the
   particular situation, additional effects may be observable.  The extent of
   these effects is described along with each of the situations.

Subtopics:

• 5.3.7.1 Storage Change and Restoration for DAT-Associated Access Exceptions
• 5.3.7.2 Modification of DAT-Table Entries
• 5.3.7.3 Trial Execution for Editing Instructions and Translate Instruction

   In  this  section,  the term "DAT-associated access exceptions" is used to
   refer  to  those   exceptions   which   may   occur   as   part   of   the
   dynamic-address-translation   process.      These   exceptions   are  page
   translation,   segment   translation,   translation   specification,   and
   addressing due to a DAT-table entry being designated at a location that is
   not  available  in  the configuration.   The first two of these exceptions
   normally cause nullification, and the last two normally cause suppression.
   Protection exceptions, including those due to  page  protection,  are  not
   considered to be DAT-associated access exceptions.

   Programming Notes:

1. The exception is recognized for a portion of a store-type operand which crosses a page boundary, and the other portion has no access exception.

2. The exception is recognized for one operand of an instruction having two storage operands (for example, an SS-format instruction or MOVE LONG), and the other operand, which is a store-type operand, has no access exception.

1. Operate on one storage page at a time

2. Perform preliminary testing to ensure that no exceptions occur for any of the required pages

3. Operate with DAT off

   When  a  valid  and  attached  DAT-table entry is changed to a value which
   would cause an exception, and when, before the TLB is cleared  of  entries
   which qualify for substitution for that entry, an attempt is made to refer
   to   storage   by  using  a  virtual  address  requiring  that  entry  for
   translation, the  contents  of  any  fields  due  to  be  changed  by  the
   instruction  are  unpredictable.    Results,  if  any, associated with the
   virtual address whose DAT-table entry was changed may be placed  in  those
   real locations originally associated with the address.  Furthermore, it is
   unpredictable  whether  or  not  an  interruption  occurs  for  an  access
   exception that was not initially  applicable.    On  some  machines,  this
   situation  may  be  reported  by means of an instruction-processing-damage
   machine check with the delayed-access-exception bit also indicated.