=========================================================================
 
     XILINX IS PROVIDING THIS DESIGN, CODE, OR INFORMATION \"AS IS\"
     SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR
     XILINX DEVICES.  BY PROVIDING THIS DESIGN, CODE, OR INFORMATION
     AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE, APPLICATION
     OR STANDARD, XILINX IS MAKING NO REPRESENTATION THAT THIS
     IMPLEMENTATION IS FREE FROM ANY CLAIMS OF INFRINGEMENT,
     AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE
     FOR YOUR IMPLEMENTATION.  XILINX EXPRESSLY DISCLAIMS ANY
     WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE
     IMPLEMENTATION, INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR
     REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF
     INFRINGEMENT, IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
     FOR A PARTICULAR PURPOSE.

     (c) Copyright 2004 Xilinx, Inc.
     All rights reserved.

======================================================================

Version Changes
================

Rev 1.0 Initial Release
Rev 1.1 Add 2VP100 Edif

Description
===========
This Zip file contains the necessary files for implementing a 350-400 MHz clock
for the left processor in the -7 Speed Grade for the 2VP20 - 2VP70 devices.

###################################################################################
# Example local clock macro design use model.
# Note: user must change netnames below to match design usage. 
# Insert local route clock macro between a given DCM and BUFGMUX.
#  _________                ___________                  ___________
# |        |               |           |                 |          |
# |  DCM   |_______________| ppc clock |_________________| BUFGMUX7P|___ cpmc405clock
# |        |               |  macro    |                 |          |
# |  dcm0t |_______________|           |_________________|          |___ plbclk
# |        |               |           |                 | BUFGMUX6S|
# |________|               |___________|                 |__________|
#
####################################################################################


Files
============

ppc_2vp20.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X0Y0 DCM in the 2VP20 device
ppc_2vp30.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X1Y0 DCM in the 2VP30 device
ppc_2vp40.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X1Y0 DCM in the 2VP40 device                     
ppc_2vp50.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X0Y0 DCM in the 2VP50 device   
ppc_2vp70.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X1Y1 DCM in the 2VP70 device
ppc_2vp100.edn       - EDIF netlist High Speed Clock macro to be used 
                          with X4Y1 DCM in the 2VP100 device
ppc_clock_macro.ucf     - Example UCF file for use with the EDIF netlists 
                          contained within this ZIP file